Expand description
AMD64 architecture definitions.
Structs§
- Amd64
- AMD64 architecture.
- Cr0
CR0control register.- Cr2
CR2control register.- Cr3
CR3control register.- Cr4
CR4control register.- Dr0
DR0debug register.- Dr1
DR1debug register.- Dr2
DR2debug register.- Dr3
DR3debug register.- Dr6
DR6debug status register.- Dr7
DR7debug control register.- Event
CpuId - Event generated when a CPUID instruction is executed.
- Event
Interrupt - Event generated when an interrupt or exception occurs.
- EventIo
- Event generated when an I/O port is accessed.
- Event
Memory Access - Event generated when monitored memory is accessed.
- Event
Singlestep - Event generated when a singlestep event occurs.
- Event
Write Control Register - Event generated when a control register is written to.
- Exception
Vector - Exception vector.
- Gdtr
- Global Descriptor Table Register (GDTR).
- GpRegisters
- General-purpose registers.
- IdtAccess
- Interrupt Descriptor Table Access Flags.
- IdtEntry
- Interrupt Descriptor Table Entry.
- Idtr
- Interrupt Descriptor Table Register (IDTR).
- Interrupt
- Information about an interrupt or exception.
- Memory
Access Flags - Flags describing a memory access event.
- MsrEfer
- Extended Feature Enable Register (EFER).
- Page
Table Entry - A page table entry in the paging structures.
- Registers
- The state of the CPU registers.
- Rflags
- The RFLAGS register.
- Segment
Access - The access rights of a segment descriptor.
- Segment
Descriptor - A segment descriptor is a data structure in a GDT or LDT that provides the processor with the size and location of a segment, as well as access control and status information. Segment descriptors are typically created by compilers, linkers, loaders, or the operating system or executive, but not application programs.
- Selector
- A segment selector is a 16-bit identifier for a segment. It does not point directly to the segment, but instead points to the segment descriptor that defines the segment.
- Translation
Entry - A single entry in the page table hierarchy during virtual address translation.
- VaTranslation
- The result of a virtual address translation process.
Enums§
- Control
Register - Control register.
- Descriptor
Table - A descriptor table.
- Descriptor
Type - Determines the type of segment descriptor.
- Event
IoDirection - Direction of the I/O port access.
- Event
Monitor - Specifies which hardware events should be monitored.
- Event
Reason - Reason for an event.
- Granularity
- Determines the scaling of the segment limit field.
- Interrupt
Type - Type of interrupt.
- Operation
Size - Determines the default length for effective addresses and operands referenced by instructions in the segment.
- Page
Table Level - The levels in the page table hierarchy.
- Paging
Mode - Supported paging modes.
Type Aliases§
- Idt
- Interrupt Descriptor Table.
- Translation
Entries - Collection of translation entries, typically used in page table walks.