Struct vl53l1_reg::structs::ShadowSystemResults

pub struct ShadowSystemResults {

    pub shadow_phasecal_result__vcsel_start: SHADOW_PHASECAL_RESULT__VCSEL_START,
    pub shadow_result__interrupt_status: SHADOW_RESULT__INTERRUPT_STATUS,
    pub shadow_result__range_status: SHADOW_RESULT__RANGE_STATUS,
    pub shadow_result__report_status: SHADOW_RESULT__REPORT_STATUS,
    pub shadow_result__stream_count: SHADOW_RESULT__STREAM_COUNT,
    pub shadow_result__dss_actual_effective_spads_sd0: SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0,
    pub shadow_result__peak_signal_count_rate_mcps_sd0: SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0,
    pub shadow_result__ambient_count_rate_mcps_sd0: SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0,
    pub shadow_result__sigma_sd0: SHADOW_RESULT__SIGMA_SD0,
    pub shadow_result__phase_sd0: SHADOW_RESULT__PHASE_SD0,
    pub shadow_result__final_crosstalk_corrected_range_mm_sd0: SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0,
    pub shadow_result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0: SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0,
    pub shadow_result__mm_inner_actual_effective_spads_sd0: SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0,
    pub shadow_result__mm_outer_actual_effective_spads_sd0: SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0,
    pub shadow_result__avg_signal_count_rate_mcps_sd0: SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0,
    pub shadow_result__dss_actual_effective_spads_sd1: SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1,
    pub shadow_result__peak_signal_count_rate_mcps_sd1: SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1,
    pub shadow_result__ambient_count_rate_mcps_sd1: SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1,
    pub shadow_result__sigma_sd1: SHADOW_RESULT__SIGMA_SD1,
    pub shadow_result__phase_sd1: SHADOW_RESULT__PHASE_SD1,
    pub shadow_result__final_crosstalk_corrected_range_mm_sd1: SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1,
    pub shadow_result__spare_0_sd1: SHADOW_RESULT__SPARE_0_SD1,
    pub shadow_result__spare_1_sd1: SHADOW_RESULT__SPARE_1_SD1,
    pub shadow_result__spare_2_sd1: SHADOW_RESULT__SPARE_2_SD1,
    pub shadow_result__spare_3_sd1: SHADOW_RESULT__SPARE_3_SD1,
    pub shadow_result__thresh_info: SHADOW_RESULT__THRESH_INFO,
    pub shadow_phasecal_result__reference_phase_hi: SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI,
    pub shadow_phasecal_result__reference_phase_lo: SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO,
}

Fields

shadow_phasecal_result__vcsel_start: SHADOW_PHASECAL_RESULT__VCSEL_START

shadow_result__interrupt_status: SHADOW_RESULT__INTERRUPT_STATUS

shadow_result__range_status: SHADOW_RESULT__RANGE_STATUS

shadow_result__report_status: SHADOW_RESULT__REPORT_STATUS

shadow_result__stream_count: SHADOW_RESULT__STREAM_COUNT

shadow_result__dss_actual_effective_spads_sd0: SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0

shadow_result__peak_signal_count_rate_mcps_sd0: SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0

shadow_result__ambient_count_rate_mcps_sd0: SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0

shadow_result__sigma_sd0: SHADOW_RESULT__SIGMA_SD0

shadow_result__phase_sd0: SHADOW_RESULT__PHASE_SD0

shadow_result__final_crosstalk_corrected_range_mm_sd0: SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0

shadow_result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0: SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0

shadow_result__mm_inner_actual_effective_spads_sd0: SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0

shadow_result__mm_outer_actual_effective_spads_sd0: SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0

shadow_result__avg_signal_count_rate_mcps_sd0: SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0

shadow_result__dss_actual_effective_spads_sd1: SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1

shadow_result__peak_signal_count_rate_mcps_sd1: SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1

shadow_result__ambient_count_rate_mcps_sd1: SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1

shadow_result__sigma_sd1: SHADOW_RESULT__SIGMA_SD1

shadow_result__phase_sd1: SHADOW_RESULT__PHASE_SD1

shadow_result__final_crosstalk_corrected_range_mm_sd1: SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1

shadow_result__spare_0_sd1: SHADOW_RESULT__SPARE_0_SD1

shadow_result__spare_1_sd1: SHADOW_RESULT__SPARE_1_SD1

shadow_result__spare_2_sd1: SHADOW_RESULT__SPARE_2_SD1

shadow_result__spare_3_sd1: SHADOW_RESULT__SPARE_3_SD1

shadow_result__thresh_info: SHADOW_RESULT__THRESH_INFO

shadow_phasecal_result__reference_phase_hi: SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI

shadow_phasecal_result__reference_phase_lo: SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO

Trait Implementations

impl Clone for ShadowSystemResults

fn clone(&self) -> ShadowSystemResults

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ShadowSystemResults

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ShadowSystemResults

fn default() -> ShadowSystemResults

Returns the “default value” for a type.

impl Entries for ShadowSystemResults

const INDEX: Index = <crate::SHADOW_PHASECAL_RESULT__VCSEL_START as crate::Entry>::INDEX

The index of the first entry.

const LEN_BYTES: usize = 82usize

The total length of the buffer necessary for I2C reading/writing.

fn write_to_slice(&self, slice: &mut [u8])

Write the entries to a single slice.

fn write<I>(&self, i2c: &mut I) -> Result<(), I::Error>where
    I: Write,

Write the entries via I2C.

fn read<I>(i2c: &mut I) -> Result<Self, I::Error>where
    I: WriteRead,

Read a new instance of the Entries struct from I2C.