Module image 

The design image: everything a slang-free runner needs, as plain data.

vj build-aot plans a design with slang, lowers it to machine code, and embeds one DesignImage in the produced .so; the runner (vj-exec) decodes it and assembles the same StateEngine + scheduler vj run assembles, without ever touching slang. vj run itself builds the same value from its own locals and instantiates it through the same code, so there is exactly one boot sequence (a second one is how “card vs sim” drift happens).

The image holds no pointer and no hash-map iteration order: it is a Vec-ordered value with a hand-written, versioned, little-endian codec (codec), so equal designs encode to identical bytes.

Modules

codec

The design image’s wire format: versioned, little-endian, and deterministic by construction (every collection is a Vec encoded in order; nothing iterates a hash map).

covdecl

The design image’s encoding of a covergroup declaration (CovGroupDecl): plain data (constants and kernel ids), so an AOT .so carries what the coverage model needs and a slang-free runner registers it with the covergroup runtime exactly as vj run does. Same conventions as codec: little-endian, collection lengths bounded by the bytes left, every enum tag checked.

verif

The verification half of a DesignImage: what the assertion engines, the sampled-value bookkeeping, the clocking-block samplers and the covergroup runtime need beyond the kernels’ machine code.

Structs

DesignImage

Everything a runner needs to assemble and run one design.

DpiImage

What a design needs of DPI-C (LRM 1800-2023 35): the C functions its imports call, and the SystemVerilog subroutines it exports to C.

DriverImage

One driver of a resolved net: its contribution cell in the bank, its strength, and its strength-ambiguity mask cell (the bits that are L/H).

DumpSignalImage

One signal $dumpvars can select (LRM 21.7): a variable or net of an instance, with the scope path the waveform shows it under. Memories and collections are not dumpable and are not listed.

ForeignImage

An instance’s foreign slots: slots own..own + targets.len() alias the listed (owner instance, owner slot) cells.

ForkBranchImage

A fork branch’s kernel (SpawnSpec::kernel indexes these).

FsmImage

An FSM named by the 40.4 pragmas, in one instance.

FsmPartImage

One piece of an FSM state vector: bits lsb..=msb of a signal.

GroupImage

A group of nets resolved together (nets: one, or several joined by inout ports).

InstanceImage

One state instance, in allocation order (the order decides each instance’s arena range and SimHandle, so it is part of the design).

KernelImage

One compiled kernel the scheduler registers as a process.

NetworkImage

Groups connected by bidirectional switches, resolved together.

PlaceImage

One signal of one instance (the bank included), as a native process addresses it.

SideSpec

One dumped port’s split of a group’s drivers, for the resolver to resolve separately (LRM 21.7.4.3.2: the test fixture’s drivers and the DUT’s own).

StmtSiteImage

One statement-coverage site (LRM 40.2.1 a): the module definition it is declared in and the source identity of the statement (the VPI side maps a statement object to its site by it, 40.5.2).

StrengthSrc

Where a MOS gate’s driver takes its strength from: the data input net (%v registry key, bit bit), lowered a level when resistive. The driver drives bit out_bit of its net. tick is the input group’s strength-change cell, which wakes the output’s resolver on a change in strength only.

SwitchImage

One bit-to-bit bidirectional switch: (group, bit) ends, where group indexes NetworkImage::groups.

TemplateImage

One unique (module, parameters) template and its state layout.

TimingImage

The design’s timing section: the options it was built under and the timing plan (gate and UDP primitives, delay lines, specify paths, timing checks, SDF annotation deltas) as an opaque, deterministic byte string. Its typed codec lives in vj-exec, which owns the code that runs it; this crate only carries and checksums it. Empty for a design with no timing constructs.

TimingOptionsImage

The run-wide timing options a design was built under (vj’s TimingOptions), in plain data. They shape what the build computed (the SDF annotations it replays, the corner it resolved, the negative-timing planning), so the runner may not change them: it refuses a conflicting flag by name instead of running a different design from the one that was built.

WireImage

One instance port connection, realized as LRM 23.3.3’s synthetic continuous assignment: a native process copying src to dst, with static sensitivity on src’s cell. The list order is the registration order (after the continuous assignments).

XWindow

A slot whose initial value is overwritten after the reset blit (a net starts at Z, but the bits a driver drives start at X).

Enums

ConductsImage

When a bidirectional switch conducts.

ControlImage

A bidirectional switch’s control terminal.

InstanceKind

Which kind of state instance an InstanceImage is.

KernelRole

What a kernel is in the registration order.

PlaceClass

A slot’s storage class, as a wire or a resolver sees it.

PortDir

A port’s direction as extended VCD records it (LRM 21.7.4.3.1): an input is dumped as the test fixture’s value (D/U/N/Z), an output as the device’s (L/H/X/T), an inout/ref port with the unknown-direction characters (0/1/?/F).

ScopeKind

A VCD scope type (LRM 1800-2023 21.7.2.1): what kind of scope a dumped signal sits in.

VcdVarType

A VCD $var type (LRM 1800-2023 21.7.2.1 var_type; parameter is not a dumped signal). A uwire is wire (21.7.2.3); logic/bit/byte and the other 2/4-state vectors are reg; Event has no value, only the marker of a trigger (21.7.2.2).

Constants

IMAGE_MAGIC

First eight bytes of an encoded image.

IMAGE_VERSION

Bumped on any change to the encoded layout.