visa_rs/enums/
assert.rs

1#![allow(overflowing_literals)]
2#![allow(non_upper_case_globals)]
3
4consts_to_enum! {
5    #[format=dbg]
6    #[repr(ViInt16)]
7    /// This specifies how to assert the interrupt.
8    ///
9    /// See [`assert_intr_signal`](crate::Instrument::assert_intr_signal)
10    ///
11    pub enum AssertIntrHow {
12        VI_ASSERT_SIGNAL            -1           r#"Send the notification via a VXI signal."#
13        VI_ASSERT_USE_ASSIGNED      0          r#"Use whatever notification method that has been assigned to the local device."#
14        VI_ASSERT_IRQ1              1          r#"
15        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
16        "#
17        VI_ASSERT_IRQ2              2          r#"
18        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
19        "#
20        VI_ASSERT_IRQ3              3          r#"
21        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
22        "#
23        VI_ASSERT_IRQ4              4          r#"
24        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
25        "#
26        VI_ASSERT_IRQ5              5          r#"
27        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
28        "#
29        VI_ASSERT_IRQ6              6          r#"
30        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
31        "#
32        VI_ASSERT_IRQ7              7          r#"
33        Send the interrupt via the specified VXI/VME IRQ line. This uses the standard VXI/VME ROAK (Release On AcKnowledge) interrupt mechanism, rather than the older VME RORA (Release On Register Access) mechanism.
34        "#
35    }
36}
37
38//pub const VI_TRIG_PROT_DEFAULT: u32 = 0;
39//pub const VI_TRIG_PROT_ON: u32 = 1;
40//pub const VI_TRIG_PROT_OFF: u32 = 2;
41//pub const VI_TRIG_PROT_SYNC: u32 = 5;
42//pub const VI_TRIG_PROT_RESERVE: u32 = 6;
43//pub const VI_TRIG_PROT_UNRESERVE: u32 = 7;
44
45consts_to_enum! {
46    #[format=dbg]
47    #[repr(ViUInt16)]
48    /// Trigger protocol to use during assertion.
49    /// * GPIB, Serial, TCPIP, USB
50    ///
51    /// VI_TRIG_PROT_DEFAULT (0)
52    ///
53    /// * VXI
54    ///
55    /// VI_TRIG_PROT_DEFAULT (0),
56    /// VI_TRIG_PROT_ON (1),
57    /// VI_TRIG_PROT_OFF (2), and
58    /// VI_TRIG_PROT_SYNC (5)
59    ///
60    /// * PXI
61    ///
62    /// VI_TRIG_PROT_RESERVE (6)
63    /// VI_TRIG_PROT_UNRESERVE (7)
64    ///
65    /// See [`assert_trigger`](crate::Instrument::assert_trigger)
66    ///
67    pub enum AssertTrigPro {
68        VI_TRIG_PROT_DEFAULT    0
69        VI_TRIG_PROT_ON         1
70        VI_TRIG_PROT_OFF        2
71        VI_TRIG_PROT_SYNC       5
72        VI_TRIG_PROT_RESERVE    6
73        VI_TRIG_PROT_UNRESERVE  7
74    }
75}
76
77//pub const VI_UTIL_ASSERT_SYSRESET: u32 = 1;
78//pub const VI_UTIL_ASSERT_SYSFAIL: u32 = 2;
79//pub const VI_UTIL_DEASSERT_SYSFAIL: u32 = 3;
80
81consts_to_enum! {
82    #[format=dbg]
83    #[repr(ViUInt16)]
84    /// Specifies the utility bus signal to assert.
85    ///
86    /// See [`assert_util_signal`](crate::Instrument::assert_util_signal)
87    ///
88    pub enum AssertBusSignal {
89        VI_UTIL_ASSERT_SYSRESET    1
90        VI_UTIL_ASSERT_SYSFAIL     2
91        VI_UTIL_DEASSERT_SYSFAIL   3
92    }
93}
visa_rs/enums/assert.rs

visa_rs/enums/
assert.rs
