virt_ic/chip/gates/
and.rs

1use std::time::Duration;
2
3use crate::{
4    chip::{ChipBuilder, ChipRunner, ChipSet, Pin, PinId, PinType},
5    generate_chip, State,
6};
7
8/// # A chip with 4 bundled "AND" gates
9///
10/// # Diagram
11/// ```
12///        ---__---
13///    A --|1   14|-- VCC
14///    B --|2   13|-- E
15///  A&B --|3   12|-- F
16///    C --|4   11|-- E&F
17///    D --|5   10|-- G
18///  C&D --|6    9|-- H
19///  GND --|7    8|-- G&H
20///        --------
21/// ```
22#[derive(Debug, Clone, Default)]
23#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
24pub struct AndGate {
25    pub vcc: Pin,
26    pub gnd: Pin,
27    pub a: Pin,
28    pub b: Pin,
29    pub ab: Pin,
30    pub c: Pin,
31    pub d: Pin,
32    pub cd: Pin,
33    pub e: Pin,
34    pub f: Pin,
35    pub ef: Pin,
36    pub g: Pin,
37    pub h: Pin,
38    pub gh: Pin,
39}
40
41impl AndGate {
42    pub const VCC: PinId = 14;
43    pub const GND: PinId = 7;
44    pub const A: PinId = 1;
45    pub const B: PinId = 2;
46    pub const AB: PinId = 3;
47    pub const C: PinId = 4;
48    pub const D: PinId = 5;
49    pub const CD: PinId = 6;
50    pub const E: PinId = 13;
51    pub const F: PinId = 12;
52    pub const EF: PinId = 11;
53    pub const G: PinId = 10;
54    pub const H: PinId = 9;
55    pub const GH: PinId = 8;
56}
57
58impl ChipBuilder<ChipSet> for AndGate {
59    fn build() -> ChipSet {
60        ChipSet::AndGate(AndGate {
61            vcc: Pin::from(PinType::Input),
62            gnd: Pin::from(PinType::Output),
63            a: Pin::from(PinType::Input),
64            b: Pin::from(PinType::Input),
65            ab: Pin::from(PinType::Output),
66            c: Pin::from(PinType::Input),
67            d: Pin::from(PinType::Input),
68            cd: Pin::from(PinType::Output),
69            e: Pin::from(PinType::Input),
70            f: Pin::from(PinType::Input),
71            ef: Pin::from(PinType::Output),
72            g: Pin::from(PinType::Input),
73            h: Pin::from(PinType::Input),
74            gh: Pin::from(PinType::Output),
75        })
76    }
77}
78
79generate_chip!(
80    AndGate,
81    vcc: AndGate::VCC,
82    gnd: AndGate::GND,
83    a: AndGate::A,
84    b: AndGate::B,
85    ab: AndGate::AB,
86    c: AndGate::C,
87    d: AndGate::D,
88    cd: AndGate::CD,
89    e: AndGate::E,
90    f: AndGate::F,
91    ef: AndGate::EF,
92    g: AndGate::G,
93    h: AndGate::H,
94    gh: AndGate::GH
95);
96
97impl ChipRunner for AndGate {
98    fn run(&mut self, _: Duration) {
99        if self.vcc.state.as_logic(3.3) == State::High {
100            self.gnd.state = State::Low;
101            self.ab.state =
102                State::from(self.a.state.as_logic(3.3).into() && self.b.state.as_logic(3.3).into());
103            self.cd.state =
104                State::from(self.c.state.as_logic(3.3).into() && self.d.state.as_logic(3.3).into());
105            self.ef.state =
106                State::from(self.e.state.as_logic(3.3).into() && self.f.state.as_logic(3.3).into());
107            self.gh.state =
108                State::from(self.g.state.as_logic(3.3).into() && self.h.state.as_logic(3.3).into());
109        }
110    }
111}
112
113/// # A chip with 3 bundled "3-Input AND" gates
114///
115/// # Diagram
116/// ```
117///            ---__---
118///        A --|1   14|-- VCC
119///        B --|2   13|-- C
120///        D --|3   12|-- A&B&C
121///        E --|4   11|-- G
122///        F --|5   10|-- H
123///    D&E&F --|6    9|-- I
124///      GND --|7    8|-- G&H&I
125///            --------
126/// ```
127#[derive(Debug, Clone, Default)]
128#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
129pub struct ThreeInputAndGate {
130    pub vcc: Pin,
131    pub gnd: Pin,
132    pub a: Pin,
133    pub b: Pin,
134    pub c: Pin,
135    pub abc: Pin,
136    pub d: Pin,
137    pub e: Pin,
138    pub f: Pin,
139    pub def: Pin,
140    pub g: Pin,
141    pub h: Pin,
142    pub i: Pin,
143    pub ghi: Pin,
144}
145
146impl ThreeInputAndGate {
147    pub const VCC: PinId = 14;
148    pub const GND: PinId = 7;
149    pub const A: PinId = 1;
150    pub const B: PinId = 2;
151    pub const C: PinId = 13;
152    pub const ABC: PinId = 12;
153    pub const D: PinId = 3;
154    pub const E: PinId = 4;
155    pub const F: PinId = 5;
156    pub const DEF: PinId = 6;
157    pub const G: PinId = 11;
158    pub const H: PinId = 10;
159    pub const I: PinId = 9;
160    pub const GHI: PinId = 8;
161}
162
163impl ChipBuilder<ChipSet> for ThreeInputAndGate {
164    fn build() -> ChipSet {
165        ChipSet::ThreeInputAndGate(ThreeInputAndGate {
166            vcc: Pin::from(PinType::Input),
167            gnd: Pin::from(PinType::Output),
168            a: Pin::from(PinType::Input),
169            b: Pin::from(PinType::Input),
170            c: Pin::from(PinType::Input),
171            abc: Pin::from(PinType::Output),
172            d: Pin::from(PinType::Input),
173            e: Pin::from(PinType::Input),
174            f: Pin::from(PinType::Input),
175            def: Pin::from(PinType::Output),
176            g: Pin::from(PinType::Input),
177            h: Pin::from(PinType::Input),
178            i: Pin::from(PinType::Input),
179            ghi: Pin::from(PinType::Output),
180        })
181    }
182}
183
184generate_chip!(
185    ThreeInputAndGate,
186    vcc: ThreeInputAndGate::VCC,
187    gnd: ThreeInputAndGate::GND,
188    a: ThreeInputAndGate::A,
189    b: ThreeInputAndGate::B,
190    c: ThreeInputAndGate::C,
191    abc: ThreeInputAndGate::ABC,
192    d: ThreeInputAndGate::D,
193    e: ThreeInputAndGate::E,
194    f: ThreeInputAndGate::F,
195    def: ThreeInputAndGate::DEF,
196    g: ThreeInputAndGate::G,
197    h: ThreeInputAndGate::H,
198    i: ThreeInputAndGate::I,
199    ghi: ThreeInputAndGate::GHI
200);
201
202impl ChipRunner for ThreeInputAndGate {
203    fn run(&mut self, _: Duration) {
204        if self.vcc.state.as_logic(3.3) == State::High {
205            self.gnd.state = State::Low;
206            self.abc.state = State::from(
207                self.a.state.as_logic(3.3).into()
208                    && self.b.state.as_logic(3.3).into()
209                    && self.c.state.as_logic(3.3).into(),
210            );
211            self.def.state = State::from(
212                self.d.state.as_logic(3.3).into()
213                    && self.e.state.as_logic(3.3).into()
214                    && self.f.state.as_logic(3.3).into(),
215            );
216            self.ghi.state = State::from(
217                self.g.state.as_logic(3.3).into()
218                    && self.h.state.as_logic(3.3).into()
219                    && self.i.state.as_logic(3.3).into(),
220            );
221        }
222    }
223}
virt_ic/chip/gates/and.rs

virt_ic/chip/gates/
and.rs
