Trait vga_framebuffer::Hardware[−][src]

pub trait Hardware {
    fn configure(
        &mut self, 
        width: u32, 
        sync_end: u32, 
        line_start: u32, 
        clock_rate: u32
    );

    fn vsync_on(&mut self);

    fn vsync_off(&mut self);

    fn write_pixels(&mut self, red: u32, green: u32, blue: u32);
}

Implement this on your microcontroller's timer object.

Required Methods

Called at start-up to configure timer.

The timer must be periodic, with period width, which is measured clock ticks (or VGA pixels), assuming the given clock rate. If you have a clock that runs at half the given rate, then double the given values.

You will receive calls to write_pixels as pixels are generated. Do not emit any pixels until the line_start timer elapses (store them in a FIFO).

The H-Sync pin must rise at the start of the loop and fall after sync_end clock ticks. We don't control it here because that would add too much latency - you must change the H-Sync GPIO pin early in the ISR yourself.

V-Sync is controlled by the current line number; you should implement vsync_on and vsync_off which this code will call at the appropriate time.

  • width - length of a line (in clock_rate pixels)
  • sync_end - elapsed time (in clock_rate pixels) before H-Sync needs to fall
  • line_start - elapsed time (in clock_rate pixels) before line_start ISR needs to fire
  • clock_rate - the pixel clock rate in Hz (e.g. 40_000_000 for 40 MHz)

Called when V-Sync needs to be high.

Called when V-Sync needs to be low.

Called word by word as pixels are calculated

Implementors