veryl_metadata/
synth.rs

1use serde::{Deserialize, Serialize};
2
3#[derive(Clone, Debug, Serialize, Deserialize)]
4#[serde(deny_unknown_fields)]
5pub struct Synth {
6    /// Default top module name. CLI `--top` overrides when supplied.
7    #[serde(default)]
8    pub top: Option<String>,
9    /// Number of worst-delay endpoints to report in the timing dump.
10    #[serde(default = "default_timing_paths")]
11    pub timing_paths: usize,
12    /// Clock frequency assumed for the dynamic-power estimate (MHz).
13    #[serde(default = "default_clock_freq")]
14    pub clock_freq: f64,
15    /// Per-cycle toggle rate assumed for combinational nets (0.0–1.0).
16    /// FF clock input is always assumed to toggle every cycle.
17    #[serde(default = "default_activity")]
18    pub activity: f64,
19    /// Built-in cell library / PDK to use.
20    #[serde(default)]
21    pub library: Library,
22    /// Smallest array, in stored bits, inferred as a RAM instead of flip-flops.
23    #[serde(default = "default_ram_min_bits")]
24    pub ram_min_bits: usize,
25    /// Largest number of distinct read addresses a RAM-inferred array may have.
26    #[serde(default = "default_ram_max_read_ports")]
27    pub ram_max_read_ports: usize,
28    /// Largest number of distinct write sites a RAM-inferred array may have.
29    #[serde(default = "default_ram_max_write_ports")]
30    pub ram_max_write_ports: usize,
31    /// Largest array, in stored bits, expanded into flip-flops after failing RAM
32    /// inference; a larger dynamically-indexed array is rejected, not expanded.
33    #[serde(default = "default_ram_max_ff_bits")]
34    pub ram_max_ff_bits: usize,
35}
36
37/// Built-in PDK library identifiers. Each variant maps to a hard-coded
38/// cell-data table in `veryl-synthesizer`.
39#[derive(Clone, Copy, Debug, Default, Serialize, Deserialize, PartialEq, Eq)]
40pub enum Library {
41    /// SkyWater SKY130 130nm PDK (sky130_fd_sc_hd, Apache 2.0).
42    #[default]
43    #[serde(rename = "sky130")]
44    Sky130,
45    /// ASU ASAP7 7nm predictive PDK (asap7sc7p5t RVT, BSD 3-Clause).
46    #[serde(rename = "asap7")]
47    Asap7,
48    /// GlobalFoundries GF180MCU 180nm PDK (gf180mcu_fd_sc_mcu7t5v0,
49    /// Apache 2.0).
50    #[serde(rename = "gf180mcu")]
51    Gf180mcu,
52    /// IHP SG13G2 130nm SiGe BiCMOS PDK (sg13g2_stdcell, Apache 2.0).
53    #[serde(rename = "ihp-sg13g2")]
54    IhpSg13g2,
55}
56
57impl Default for Synth {
58    fn default() -> Self {
59        // Route through serde so the `default =` fn pointers are honoured
60        // — a naive derive(Default) would zero out the numeric fields.
61        toml::from_str("").unwrap()
62    }
63}
64
65fn default_timing_paths() -> usize {
66    1
67}
68
69fn default_clock_freq() -> f64 {
70    100.0
71}
72
73fn default_activity() -> f64 {
74    0.1
75}
76
77fn default_ram_min_bits() -> usize {
78    1024
79}
80
81fn default_ram_max_read_ports() -> usize {
82    16
83}
84
85fn default_ram_max_write_ports() -> usize {
86    8
87}
88
89fn default_ram_max_ff_bits() -> usize {
90    1 << 16
91}
veryl_metadata/synth.rs

veryl_metadata/
synth.rs
