verilog/
ast.rs

1use std::collections::BTreeSet;
2
3#[derive(Clone, Debug, Eq, Hash, PartialEq)]
4pub struct Code(pub Vec<Toplevel>);
5
6pub type Arg = (Ident, Option<Dir>, Option<i32>);
7
8#[derive(Clone, Debug, Eq, Hash, PartialEq)]
9pub enum Toplevel {
10    Module(Ident, Vec<Arg>, Vec<Decl>),
11}
12
13#[derive(Clone, Debug, Eq, Hash, PartialEq)]
14pub struct Ident(pub String);
15
16#[derive(Clone, Debug, Eq, Hash, PartialEq)]
17pub enum Dir {
18    In,
19    Out,
20}
21
22#[derive(Clone, Debug, Eq, Hash, PartialEq)]
23pub enum Edge {
24    Pos,
25    Neg,
26}
27
28#[derive(Clone, Debug, Eq, Hash, PartialEq)]
29pub struct EdgeRef(pub Ident, pub Edge);
30
31#[derive(Clone, Debug, Eq, Hash, PartialEq)]
32pub enum Decl {
33    InnerArg(Vec<Arg>),
34    Reg(Ident, Vec<Expr>),
35    Wire(Ident, Vec<Expr>, Option<Expr>),
36    Let(Ident, Ident, Vec<(Ident, Expr)>),
37    Const(Ident, Expr),
38    Always(EdgeRef, SeqBlock),
39}
40
41#[derive(Clone, Debug, Eq, Hash, PartialEq)]
42pub struct SeqBlock(pub Vec<Seq>);
43
44#[derive(Copy, Clone, Debug, Eq, Hash, PartialEq)]
45pub enum BlockType {
46    Blocking,
47    NonBlocking,
48    Static,
49}
50
51#[derive(Clone, Debug, Eq, Hash, PartialEq)]
52pub enum Seq {
53    If(Expr, SeqBlock, Option<SeqBlock>),
54    Set(BlockType, Ident, Expr),
55    SetIndex(BlockType, Ident, Expr, Expr),
56    SetRange(BlockType, Ident, Expr, Expr, Expr),
57    Match(Expr, Vec<(Vec<Expr>, SeqBlock)>),
58
59    While(Expr, SeqBlock),
60    Loop(SeqBlock),
61    Async(SeqBlock),
62    FsmCaseTransition(Ident),
63    Fsm(Vec<(Ident, SeqBlock)>),
64    Yield,
65    Await(Expr),
66
67    FsmCase(Vec<(Vec<i32>, SeqBlock)>),
68    FsmTransition(u32),
69}
70
71//#[derive(Clone, Debug, Eq, Hash, PartialEq)]
72//pub struct CombBlock(pub Vec<Comb>);
73//
74//#[derive(Clone, Debug, Eq, Hash, PartialEq)]
75//pub enum Comb {
76//    If(Expr, CombBlock, Option<CombBlock>),
77//    Assign(Ident, Expr),
78//}
79
80#[derive(Clone, Debug, Eq, Hash, PartialEq)]
81pub enum Op {
82    Add,
83    Sub,
84    Mul,
85    Div,
86    Eq,
87    Lte,
88    Gte,
89    And,
90    Or,
91    Lt,
92    Gt,
93    Ne,
94    BinOr,
95    BinAnd,
96    LShift,
97    RShift,
98}
99
100#[derive(Clone, Debug, Eq, Hash, PartialEq)]
101pub enum UnaryOp {
102    Not,
103}
104
105#[derive(Clone, Debug, Eq, Hash, PartialEq)]
106pub enum Expr {
107    Ref(Ident),
108    Slice(Ident, Box<Expr>, Option<Box<Expr>>),
109    Ternary(Box<Expr>, Box<Expr>, Box<Expr>),
110    Concat(Vec<Expr>),
111    Repeat(Box<Expr>, Box<Expr>),
112    Arith(Op, Box<Expr>, Box<Expr>),
113    Unary(UnaryOp, Box<Expr>),
114    Num(i32),
115    Placeholder,
116
117    FsmEq(BTreeSet<i32>),
118    FsmNe(BTreeSet<i32>),
119}
120
121impl Expr {
122    pub fn to_i32(&self) -> i32 {
123        match *self {
124            Expr::Num(value) => value,
125            _ => {
126                panic!("Called to_i32 on non-Num.")
127            }
128        }
129    }
130}
verilog/ast.rs

verilog/
ast.rs
