prefetch_vector

velesdb_core::simd

Function prefetch_vector 

Source 
pub fn prefetch_vector(vector: &[f32])
Expand description

Prefetches a vector into L1 cache (T0 hint) for upcoming SIMD operations.

§Platform Support

  • x86_64: Uses _mm_prefetch with _MM_HINT_T0 (all cache levels) ✅
  • aarch64: No-op (see limitation below) ⚠️
  • Other: No-op (graceful degradation)

§ARM64 Limitation (rust-lang/rust#117217)

ARM NEON prefetch intrinsics (__prefetch) require the unstable feature stdarch_aarch64_prefetch which is not available on stable Rust. When this feature stabilizes, we can enable prefetch for ARM64 platforms (Apple Silicon, ARM servers) for an estimated +10-20% performance gain.

Tracking: https://github.com/rust-lang/rust/issues/117217

§Safety

This function is safe because prefetch instructions are hints and cannot cause memory faults even with invalid addresses.

§Performance

On x86_64: Reduces cache miss latency by ~50-100 cycles when vectors are prefetched 4-16 iterations ahead of actual use.