vrl/
common.rs

1use std::ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Neg, Sub, SubAssign};
2
3/// Represents a packed vector containing [`ELEMENTS`](SIMDVector::ELEMENTS)
4/// values of type [`Element`].
5///
6/// Converting [`Element`] to [`SIMDVector`] works as `broadcast`, i.e. assigns
7/// the converting value to all elements of the vector.
8///
9/// [`Default::default`] initializes all elements of vector with zero.
10///
11/// All arithmetic operations ([`Neg`], [`Add`], etc) are applied vertically, i.e. "elementwise".
12///
13/// [`Element`]: Self::Element
14pub trait SIMDVector
15where
16    Self: From<Self::Underlying>
17        + Default
18        + Neg<Output = Self>
19        + Add<Self>
20        + Add<Self::Element>
21        + Sub<Self>
22        + Sub<Self::Element>
23        + Mul<Self>
24        + Mul<Self::Element>
25        + Div<Self>
26        + Div<Self::Element>
27        + AddAssign<Self>
28        + AddAssign<Self::Element>
29        + SubAssign<Self>
30        + SubAssign<Self::Element>
31        + MulAssign<Self>
32        + MulAssign<Self::Element>
33        + DivAssign<Self>
34        + DivAssign<Self::Element>, // + [Self::Element; Self::ELEMENTS]
35    Self::Underlying: From<Self>,
36    Self::Element: Add<Self> + Sub<Self> + Mul<Self> + Div<Self>,
37{
38    /// Underlying intrinsic type or tuple of types implementing [`SIMDVector`].
39    type Underlying;
40
41    /// Type of a single element of [`SIMDVector`].
42    type Element;
43
44    /// Number of elements in [`SIMDVector`].
45    const ELEMENTS: usize;
46}