1#![no_std]
47#![warn(missing_docs)]
48
49pub mod registers;
51
52#[cfg(feature = "defmt")]
53use defmt::Format;
54use embedded_hal_async::delay::DelayNs;
55use crate::registers::{Filter, IDACMagnitude, IDACMux, Mode, PGAGain, ReferenceInput, StatusRegisterValue, RegisterAddress, ByteRepresentation, ConfigurationRegisters};
56use embedded_hal::digital::InputPin;
57use embedded_hal::spi::Operation;
58use embedded_hal_async::digital::Wait;
59use embedded_hal_async::spi::SpiDevice;
60use embassy_futures::select::{select, Either};
61
62
63pub enum WaitStrategy<INPUT: InputPin + Wait> {
65 UseDrdyPin(INPUT),
67 Delay
69}
70
71#[derive(Debug, Clone, Copy)]
73#[cfg_attr(feature = "defmt", derive(Format))]
74pub enum Command {
75 NOP,
77 WAKEUP,
79 POWERDOWN,
81 RESET,
83 START,
85 STOP,
87 SYOCAL,
89 SYGCAL,
91 SFOCAL,
93 RDATA,
95 RREG {
97 address: u8,
99 n: u8
101 },
102 WREG {
104 address: u8,
106 n: u8
108 },
109}
110
111impl Command {
112 fn bits(&self) -> (u8, Option<u8>) {
113 match self {
114 Command::NOP => (0b0000_0000, None),
115 Command::WAKEUP => (0b0000_0010, None),
116 Command::POWERDOWN => (0b0000_0100, None),
117 Command::RESET => (0b0000_0110, None),
118 Command::START => (0b0000_1000, None),
119 Command::STOP => (0b0000_1010, None),
120 Command::SYOCAL => (0b0001_0110, None),
121 Command::SYGCAL => (0b0001_0111, None),
122 Command::SFOCAL => (0b0001_1001, None),
123 Command::RDATA => (0b0001_0010, None),
124 Command::RREG { address, n } => (0b0010_0000 | (address & 0b1_1111), Some(n & 0b1_1111)),
125 Command::WREG { address, n } => (0b0100_0000 | (address & 0b1_1111), Some(n & 0b1_1111)),
126 }
127 }
128}
129
130#[derive(Debug, Clone, Copy)]
132#[cfg_attr(feature = "defmt", derive(Format))]
133pub enum ADS124S08Error {
134 SPIError,
136 ReadTimeoutError,
138 WriteTimeoutError,
140 UnableToRestorePreviousConfigurationWhileHandlingError,
142 InvalidRegisterValue(RegisterAddress, u8),
144 InvalidCommand,
146 NotInTransaction,
148 ConfigurationReadBackFailed(RegisterAddress)
150}
151
152#[derive(Debug, Copy, Clone)]
154#[cfg_attr(feature = "defmt", derive(Format))]
155pub struct Code {
156 pub data: [u8; 3],
158 pub reference: ReferenceInput,
160 pub pga_enabled: bool,
162 pub gain: PGAGain,
164 pub idac1_magnitude: Option<IDACMagnitude>,
166 pub idac2_magnitude: Option<IDACMagnitude>,
168}
169
170impl Code {
171 pub fn new(data: [u8; 3], reference: ReferenceInput, pga_enabled: bool, gain: PGAGain, idac1_magnitude: Option<IDACMagnitude>, idac2_magnitude: Option<IDACMagnitude>) -> Self {
173 Code {
174 data,
175 reference,
176 pga_enabled,
177 gain,
178 idac1_magnitude,
179 idac2_magnitude,
180 }
181 }
182
183 pub fn from_code(code: i32, reference: ReferenceInput, pga_enabled: bool, gain: PGAGain, idac1_magnitude: Option<IDACMagnitude>, idac2_magnitude: Option<IDACMagnitude>) -> Self {
185 let original: [u8; 4] = code.to_be_bytes();
186 let result: [u8; 3] = original[1..].try_into().unwrap();
187
188 Code {
189 data: result,
190 reference,
191 pga_enabled,
192 gain,
193 idac1_magnitude,
194 idac2_magnitude,
195 }
196 }
197
198 pub fn over_fs(&self) -> bool {
200 self.data[0] == 0x7f && self.data[1] == 0xff && self.data[2] == 0xff
201 }
202
203 pub fn below_fs(&self) -> bool {
205 self.data[0] == 0x80 && self.data[1] == 0x00 && self.data[2] == 0x00
206 }
207
208 pub fn code(&self) -> i32 {
210 let fill = if self.data[0] & 0x80 == 0x80 { 0xff } else { 0x00 };
211
212 i32::from_be_bytes([fill, self.data[0], self.data[1], self.data[2]])
213 }
214
215 pub fn internally_referenced_voltage(&self) -> f32 {
217 self.externally_referenced_voltage(0.0, 2.5)
218 }
219
220 pub fn externally_referenced_voltage(&self, v_ref_n: f32, v_ref_p: f32) -> f32 {
222 let code = self.code();
223 let v_ref = v_ref_p - v_ref_n;
224 let gain = if self.pga_enabled { self.gain.value() as f32 } else { 1.0 };
225 let v_per_lsb = (2.0 * v_ref) / (gain * (1 << 24) as f32);
226
227 code as f32 * v_per_lsb
228 }
229
230 pub fn ratiometric_resistance(&self, r_ref: f32) -> f32 {
232 let code = self.code() as f32;
233 let gain = if self.pga_enabled { self.gain.value() as f32 } else { 1.0 };
234 (r_ref * code) / ((1 << 23) as f32 * gain)
235 }
236}
237
238macro_rules! define_read_write_register_ops {
239 ($base_name:ident, $reg:ident, $reg_type:ty) => {
240 paste::item! {
241 #[allow(dead_code)]
243 #[doc = concat!("Read the ", stringify!($base_name), " register")]
244 pub async fn [<read_ $base_name _reg>]<'a>(&mut self) -> Result<$reg_type, ADS124S08Error>
245 {
246 let bits = self.read_reg(registers::RegisterAddress::$reg).await?;
247 let res = $reg_type::from_bits(bits).ok_or(ADS124S08Error::InvalidRegisterValue(registers::RegisterAddress::$reg, bits));
248 if res.is_ok() {
249 let d = res.unwrap();
250 self.read_configuration_registers.$base_name = d.clone();
251 return Ok(d)
252 }
253
254 res
255 }
256
257 #[allow(dead_code)]
259 #[doc = concat!("Write the ", stringify!($base_name), " register")]
260 pub async fn [<write_ $base_name _reg>]<'a>(&mut self, value: $reg_type) -> Result<(), ADS124S08Error>
261 {
262 self.write_reg(registers::RegisterAddress::$reg, value.bits()).await?;
263 self.configuration_registers.$base_name = value;
264 self.read_configuration_registers.$base_name = value;
265 Ok(())
266 }
267
268 #[allow(dead_code)]
270 #[doc = concat!("Swap the ", stringify!($base_name), " register and return the previous value")]
271 pub async fn [<swap_ $base_name _reg>]<'a>(&mut self, value: $reg_type) -> Result<$reg_type, ADS124S08Error>
272 {
273 let current = self.[<read_ $base_name _reg>]().await?;
274 self.[<write_ $base_name _reg>](value).await?;
275 Ok(current)
276 }
277 }
278 };
279}
280
281macro_rules! define_read_only_register_ops {
282 ($base_name:ident, $reg:ident, $reg_type:ty) => {
283 paste::item! {
284 #[allow(dead_code)]
286 #[doc = concat!("Read the ", stringify!($base_name), " register")]
287 async fn [<read_ $base_name _reg>]<'a>(&mut self) -> Result<$reg_type, ADS124S08Error>
288 {
289 let bits = self.read_reg(registers::RegisterAddress::$reg).await?;
290 $reg_type::from_bits(bits).ok_or(ADS124S08Error::InvalidRegisterValue(registers::RegisterAddress::$reg, bits))
291 }
292 }
293 };
294}
295
296pub struct ADS124S08<SpiDevT: SpiDevice, InputPinT: InputPin + Wait, D: DelayNs> {
298 spi: SpiDevT,
299 wait_strategy: WaitStrategy<InputPinT>,
300 delay: D,
301 configuration_registers: ConfigurationRegisters,
302
303 read_configuration_registers: ConfigurationRegisters,
304}
305
306impl<SpiDevT: SpiDevice, InputPinT: InputPin + Wait, D: DelayNs> ADS124S08<SpiDevT, InputPinT, D> {
307 pub fn new(spi: SpiDevT, wait_strategy: WaitStrategy<InputPinT>, delay: D) -> ADS124S08<SpiDevT, InputPinT, D> {
310 ADS124S08 {
311 spi,
312 wait_strategy,
313 delay,
314 configuration_registers: ConfigurationRegisters::default(),
315 read_configuration_registers: ConfigurationRegisters::default(),
316 }
317 }
318
319 pub async fn measure_single_ended<'a>(&mut self, input: registers::Mux, reference_input: ReferenceInput) -> Result<Code, ADS124S08Error> {
321 let mut config = self.configuration_registers.clone();
323
324 config.inpmux.p = input;
325 config.inpmux.n = registers::Mux::AINCOM;
326 config.pga.enable = false;
327 config.pga.gain = registers::PGAGain::Gain1;
328 config.idacmag.imag = registers::IDACMagnitude::Off;
329 config.idacmux.i2mux = registers::IDACMux::Disconnected;
330 config.idacmux.i1mux = registers::IDACMux::Disconnected;
331 config.refctrl.refsel = reference_input;
332
333 config = self.swap_all_configuration_registers(config).await?;
334
335 let res = self.start_wait_for_drdy_read_and_stop().await;
336 self.swap_all_configuration_registers(config).await?;
337
338 res
339 }
340
341 pub async fn measure_ratiometric_low_side<'a>(
343 &mut self,
344 input_p: registers::Mux,
345 input_n: registers::Mux,
346 idac1: registers::IDACMux,
347 idac2: registers::IDACMux,
348 reference_input: registers::ReferenceInput,
349 idac_magnitude: registers::IDACMagnitude,
350 gain: registers::PGAGain,
351 ) -> Result<Code, ADS124S08Error> {
352 let mut config = self.configuration_registers.clone();
355
356 config.inpmux.p = input_p;
357 config.inpmux.n = input_n;
358 config.idacmag.imag = idac_magnitude;
359 config.idacmux.i2mux = idac2;
360 config.idacmux.i1mux = idac1;
361 config.refctrl.n_refp_buf = true;
362 config.refctrl.n_refn_buf = true;
363 config.refctrl.refsel = reference_input;
364 config.refctrl.refcon = registers::InternalVoltageReferenceConfiguration::OnButPowersDown;
365 config.pga.enable = true;
366 config.pga.gain = gain;
367 config.datarate.mode = Mode::Continuous;
368 config.datarate.rate = registers::DataRate::SPS20;
369 config.datarate.filter = Filter::SINC3;
370
371 config = self.swap_all_configuration_registers(config).await?;
372
373 self.start_conversion().await?;
374let res = self.start_wait_for_drdy_read_and_stop().await;
376
377 self.swap_all_configuration_registers(config).await?;
378
379 res
380 }
381
382 pub async fn measure_differential<'a>(
384 &mut self,
385 input_p: registers::Mux,
386 input_n: registers::Mux,
387 reference_input: registers::ReferenceInput,
388 gain: registers::PGAGain,
389 ) -> Result<Code, ADS124S08Error> {
390 let mut config = self.configuration_registers.clone();
391
392 config.inpmux.p = input_p;
393 config.inpmux.n = input_n;
394 config.pga.enable = gain != PGAGain::Gain1;
395 config.pga.gain = gain;
396 config.idacmag.imag = IDACMagnitude::Off;
397 config.idacmux.i2mux = IDACMux::Disconnected;
398 config.idacmux.i1mux = IDACMux::Disconnected;
399 config.refctrl.refsel = reference_input;
400
401 config = self.swap_all_configuration_registers(config).await?;
403
404 let res = self.start_wait_for_drdy_read_and_stop().await;
406
407 self.swap_all_configuration_registers(config).await?;
409
410 res
411 }
412
413 pub async fn read_dvdd_by_4<'a>(&mut self) -> Result<Code, ADS124S08Error> {
415 let mut new_config = self.configuration_registers.sys.clone();
416 new_config.sys_mon = registers::SystemMonitorConfiguration::DvddBy4Measurement;
417 new_config.sendstat = true;
418 new_config.crc = true;
419
420 let prev_config = self.swap_sys_reg(
421 new_config
422 ).await?;
423
424 let mut new_refctl = self.configuration_registers.refctrl.clone();
425 new_refctl.refsel = registers::ReferenceInput::Internal;
426 new_refctl.refcon = registers::InternalVoltageReferenceConfiguration::AlwaysOn;
427
428 let prev_refctl = self.swap_refctrl_reg(new_refctl).await?;
429
430 let _curr_cfg_read = self.read_sys_reg().await?;
431 let res = self.start_wait_for_drdy_and_read().await;
434
435 self.write_sys_reg(prev_config).await?;
436 self.write_refctrl_reg(prev_refctl).await?;
437
438 res
439 }
440
441 pub async fn read_avdd_by_4<'a>(&mut self) -> Result<Code, ADS124S08Error> {
443 let mut new_config = self.configuration_registers.sys.clone();
444 new_config.sys_mon = registers::SystemMonitorConfiguration::AvddMinusAvssBy4Measurement;
445 new_config.sendstat = true;
446 new_config.crc = true;
447
448 let prev_config = self.swap_sys_reg(
449 new_config
450 ).await?;
451
452 let mut new_refctl = self.configuration_registers.refctrl.clone();
453 new_refctl.refsel = registers::ReferenceInput::Internal;
454 new_refctl.refcon = registers::InternalVoltageReferenceConfiguration::AlwaysOn;
455
456 let prev_refctl = self.swap_refctrl_reg(new_refctl).await?;
457
458 let res = self.start_wait_for_drdy_read_and_stop().await;
459
460 self.write_sys_reg(prev_config).await?;
461 self.write_refctrl_reg(prev_refctl).await?;
462
463 res
464 }
465
466
467 pub async fn read_temperature<'a>(&mut self) -> Result<Code, ADS124S08Error> {
469 let mut new_config = self.configuration_registers.sys.clone();
470 new_config.sys_mon = registers::SystemMonitorConfiguration::InternalTemperatureSensor;
471 new_config.sendstat = true;
472 new_config.crc = true;
473
474 let prev_config = self.swap_sys_reg(
475 new_config
476 ).await?;
477
478 let mut new_refctl = self.configuration_registers.refctrl.clone();
479 new_refctl.refsel = registers::ReferenceInput::Internal;
480 new_refctl.refcon = registers::InternalVoltageReferenceConfiguration::AlwaysOn;
481
482 let prev_refctl = self.swap_refctrl_reg(new_refctl).await?;
483
484 let res = self.start_wait_for_drdy_read_and_stop().await;
485
486 self.write_sys_reg(prev_config).await?;
487 self.write_refctrl_reg(prev_refctl).await?;
488
489 res
490 }
491
492 pub async fn read_device_id<'a>(&mut self) -> Result<registers::DeviceId, ADS124S08Error> {
494 self.read_id_reg().await
495 }
496
497 pub async fn configure_measurement<'a>(&mut self, configuration_registers: ConfigurationRegisters) -> Result<(), ADS124S08Error> {
500 self.configuration_registers = configuration_registers;
501 self.write_modified_configuration_registers_to_device().await
502 }
503
504 pub async fn start_conversion<'a>(&mut self) -> Result<(), ADS124S08Error> {
506 self.write_command(Command::START).await
507 }
508
509 pub async fn stop_conversion<'a>(&mut self) -> Result<(), ADS124S08Error> {
511 self.write_command(Command::STOP).await
512 }
513
514 pub async fn wait_for_drdy_and_read<'a>(&mut self) -> Result<Code, ADS124S08Error> {
516 self.wait_for_drdy().await?;
517 self.read_data().await
518 }
519
520 pub async fn start_wait_for_drdy_and_read<'a>(&mut self) -> Result<Code, ADS124S08Error> {
522 self.start_conversion().await?;
523 self.wait_for_drdy().await?;
524 self.read_data().await
525 }
526
527 pub async fn start_wait_for_drdy_read_and_stop<'a>(&mut self) -> Result<Code, ADS124S08Error> {
529 self.start_conversion().await?;
530 self.wait_for_drdy().await?;
531
532 let d = self.read_data().await?;
533
534 self.stop_conversion().await?;
535
536 Ok(d)
537 }
538
539 pub async fn read_n_sample_average<'a>(&mut self, n: i32) -> Result<Code, ADS124S08Error> {
541 let mut sum = 0;
542
543 for _ in 0..n {
544 self.wait_for_drdy().await?;
545 sum += self.read_data().await?.code();
546 }
547
548 Ok(Code::from_code(sum / n, ReferenceInput::Internal, false, PGAGain::Gain1, None, None))
549 }
550
551 pub async fn read_configuration_registers<'a>(&mut self) -> Result<ConfigurationRegisters, ADS124S08Error> {
553 self.read_configuration_registers_from_device().await?;
554 Ok(self.read_configuration_registers.clone())
555 }
556
557 pub async fn wait_for_drdy<'a>(&mut self) -> Result<(), ADS124S08Error> {
561 match &mut self.wait_strategy {
562 WaitStrategy::UseDrdyPin(drdy_input) => {
563 let timeout_ms = self.configuration_registers.datarate.rate.sample_period_ms() * 3; let wait_future = drdy_input.wait_for_low();
566 let timeout_future = async {
567 self.delay.delay_ms(timeout_ms).await;
568 Err(ADS124S08Error::ReadTimeoutError)
569 };
570
571 match select(wait_future, timeout_future).await {
572 Either::First(result) => result.map_err(|_e| ADS124S08Error::SPIError),
573 Either::Second(timeout_err) => timeout_err,
574 }
575 },
576 WaitStrategy::Delay => {
578 let base_period = self.configuration_registers.datarate.rate.sample_period_ms();
579 let margin = core::cmp::max(base_period * 5 / 100, 1); let delay_ms = base_period + margin;
581 self.delay.delay_ms(delay_ms).await;
582 Ok(())
583 },
584 }
585 }
586
587 async fn swap_all_configuration_registers<'a>(&mut self, configuration_registers: ConfigurationRegisters) -> Result<ConfigurationRegisters, ADS124S08Error> {
588 let prev = self.configuration_registers.clone();
589 self.configuration_registers = configuration_registers;
590 let res = self.write_modified_configuration_registers_to_device().await;
591
592 if res.is_err() {
593 self.configuration_registers = prev;
594 self.write_all_configuration_registers_to_device().await?;
595 return Err(ADS124S08Error::UnableToRestorePreviousConfigurationWhileHandlingError);
596 }
597
598 Ok(prev)
599 }
600
601 async fn read_configuration_registers_from_device<'a>(&mut self) -> Result<(), ADS124S08Error> {
602 self.configuration_registers.inpmux = self.read_inpmux_reg().await?;
603 self.configuration_registers.pga = self.read_pga_reg().await?;
604 self.configuration_registers.datarate = self.read_datarate_reg().await?;
605 self.configuration_registers.refctrl = self.read_refctrl_reg().await?;
606 self.configuration_registers.idacmag = self.read_idacmag_reg().await?;
607 self.configuration_registers.idacmux = self.read_idacmux_reg().await?;
608 self.configuration_registers.vbias = self.read_vbias_reg().await?;
609 self.configuration_registers.sys = self.read_sys_reg().await?;
610
611 Ok(())
612 }
613
614 async fn write_all_configuration_registers_to_device<'a>(&mut self) -> Result<(), ADS124S08Error> {
615 self.write_inpmux_reg(self.configuration_registers.inpmux).await?;
616 self.write_pga_reg(self.configuration_registers.pga).await?;
617 self.write_datarate_reg(self.configuration_registers.datarate).await?;
618 self.write_refctrl_reg(self.configuration_registers.refctrl).await?;
619 self.write_idacmag_reg(self.configuration_registers.idacmag).await?;
620 self.write_idacmux_reg(self.configuration_registers.idacmux).await?;
621 self.write_vbias_reg(self.configuration_registers.vbias).await?;
622 self.write_sys_reg(self.configuration_registers.sys).await?;
623
624 Ok(())
625 }
626
627 async fn write_modified_configuration_registers_to_device<'a>(&mut self) -> Result<(), ADS124S08Error> {
628 if self.configuration_registers.inpmux != self.read_configuration_registers.inpmux {
629 self.write_inpmux_reg(self.configuration_registers.inpmux).await?;
630 }
631
632 if self.configuration_registers.pga != self.read_configuration_registers.pga {
633 self.write_pga_reg(self.configuration_registers.pga).await?;
634 }
635
636 if self.configuration_registers.datarate != self.read_configuration_registers.datarate {
637 self.write_datarate_reg(self.configuration_registers.datarate).await?;
638 }
639
640 if self.configuration_registers.refctrl != self.read_configuration_registers.refctrl {
641 self.write_refctrl_reg(self.configuration_registers.refctrl).await?;
642 }
643
644 if self.configuration_registers.idacmag != self.read_configuration_registers.idacmag {
645 self.write_idacmag_reg(self.configuration_registers.idacmag).await?;
646 }
647
648 if self.configuration_registers.idacmux != self.read_configuration_registers.idacmux {
649 self.write_idacmux_reg(self.configuration_registers.idacmux).await?;
650 }
651
652 if self.configuration_registers.vbias != self.read_configuration_registers.vbias {
653 self.write_vbias_reg(self.configuration_registers.vbias).await?;
654 }
655
656 if self.configuration_registers.sys != self.read_configuration_registers.sys {
657 self.write_sys_reg(self.configuration_registers.sys).await?;
658 }
659
660 Ok(())
661 }
662
663 define_read_only_register_ops!(id, ID, registers::DeviceId);
664 define_read_only_register_ops!(status, STATUS, registers::StatusRegisterValue);
665 define_read_write_register_ops!(inpmux, INPMUX, registers::InputMultiplexerRegister);
666 define_read_write_register_ops!(pga, PGA, registers::PgaRegister);
667 define_read_write_register_ops!(datarate, DATARATE, registers::DataRateRegister);
668 define_read_write_register_ops!(refctrl, REF, registers::ReferenceControlRegister);
669 define_read_write_register_ops!(idacmag, IDACMAG, registers::IDACMagnitudeRegister);
670 define_read_write_register_ops!(idacmux, IDACMUX, registers::IDACMultiplexerRegister);
671 define_read_write_register_ops!(vbias, VBIAS, registers::SensorBiasingRegister);
672 define_read_write_register_ops!(sys, SYS, registers::SystemControlRegister);
673
674 pub async fn read_data<'a>(&mut self) -> Result<Code, ADS124S08Error> {
676 self.write_command(Command::RDATA).await?;
677
678 if self.configuration_registers.sys.sendstat {
679 let mut status_buf = [0x00];
680 self.spi_read(&mut status_buf).await?;
681
682 let _ = StatusRegisterValue::from_bits(status_buf[0]);
683 }
685
686 let mut data_buf = [0x00; 3];
687 self.spi_read(&mut data_buf).await?;
688
689 if self.configuration_registers.sys.crc {
692 let mut crc_buf = [0x00];
693 self.spi_read(&mut crc_buf).await?;
694 }
696
697 Ok(Code {
698 data: data_buf,
699 reference: self.configuration_registers.refctrl.refsel,
700 pga_enabled: self.configuration_registers.pga.enable,
701 gain: self.configuration_registers.pga.gain,
702 idac1_magnitude: if self.configuration_registers.idacmux.i1mux != IDACMux::Disconnected { Some(self.configuration_registers.idacmag.imag) } else { None },
703 idac2_magnitude: if self.configuration_registers.idacmux.i2mux != IDACMux::Disconnected { Some(self.configuration_registers.idacmag.imag) } else { None },
704 })
705 }
706
707 async fn write_reg<'a>(&mut self, reg: RegisterAddress, value: u8) -> Result<(), ADS124S08Error> {
708 let command = Command::WREG { address: reg.addr(), n: 0 };
709
710 let (byte0, byte1) = command.bits();
711
712 if byte1.is_some() {
713 self.spi_transaction(&mut [Operation::DelayNs(100000), Operation::Write(&[byte0, byte1.unwrap()]), Operation::Write(&[value]), Operation::DelayNs(100000)]).await.map_err(|_e| ADS124S08Error::SPIError)?;
714 } else {
715 self.spi_transaction(&mut [Operation::DelayNs(100000), Operation::Write(&[byte0]), Operation::Write(&[value]), Operation::DelayNs(100000)]).await.map_err(|_e| ADS124S08Error::SPIError)?;
716 }
717
718 Ok(())
726 }
727
728 async fn read_reg<'a>(&mut self, register: RegisterAddress) -> Result<u8, ADS124S08Error> {
729 let command = Command::RREG { address: register.addr(), n: 0 };
730 let mut reg_buf = [0x00];
731
732 let (byte0, byte1) = command.bits();
733
734 if byte1.is_some() {
735 self.spi_transaction(&mut [Operation::DelayNs(100), Operation::Write(&[byte0, byte1.unwrap()]), Operation::Read(&mut reg_buf), Operation::DelayNs(100)]).await.map_err(|_e| ADS124S08Error::SPIError)?;
736 } else {
737 self.spi_transaction(&mut [Operation::DelayNs(100), Operation::Write(&[byte0]), Operation::Read(&mut reg_buf), Operation::DelayNs(100)]).await.map_err(|_e| ADS124S08Error::SPIError)?;
738 }
739
740Ok(reg_buf[0])
743 }
744
745 pub async fn reset<'a>(&mut self) -> Result<(), ADS124S08Error> {
747 self.write_command(Command::RESET).await?;
748 self.delay.delay_ms(100).await;
749 self.read_configuration_registers_from_device().await?;
750
751 Ok(())
752 }
753
754 async fn write_command<'a>(&mut self, command: Command) -> Result<(), ADS124S08Error> {
755 let (byte0, byte1) = command.bits();
756
757 if byte1.is_some() {
758 self.spi_write(&[byte0, byte1.unwrap()]).await?;
759 } else {
760 self.spi_write(&[byte0]).await?;
761 }
762
763 Ok(())
766 }
767
768 async fn spi_read<'a>(&mut self, buffer: &mut [u8]) -> Result<(), ADS124S08Error> {
769 let ret = self.spi.transaction(&mut[Operation::DelayNs(100), Operation::Read(buffer), Operation::DelayNs(100)]).await.map_err(|_e| ADS124S08Error::SPIError);
770
771 ret
772
773}
791
792 async fn spi_write<'a>(&mut self, buffer: &[u8]) -> Result<(), ADS124S08Error> {
793 let ret = self.spi.transaction(&mut[Operation::DelayNs(100), Operation::Write(buffer), Operation::DelayNs(100)]).await.map_err(|_e| ADS124S08Error::SPIError);
794
795 ret
796
797 }
814
815 async fn spi_transaction<'a>(&mut self, ops: &mut [Operation<'_, u8>]) -> Result<(), ADS124S08Error> {
816 let ret = self.spi.transaction(ops).await.map_err(|_e| ADS124S08Error::SPIError);
817
818 ret
819 }
820}