va108xx/sysconfig/
peripheral_clk_enable.rs1#[doc = "Register `PERIPHERAL_CLK_ENABLE` reader"]
2pub type R = crate::R<PeripheralClkEnableSpec>;
3#[doc = "Register `PERIPHERAL_CLK_ENABLE` writer"]
4pub type W = crate::W<PeripheralClkEnableSpec>;
5#[doc = "Field `PORTA` reader - Enable PORTA clock"]
6pub type PortaR = crate::BitReader;
7#[doc = "Field `PORTA` writer - Enable PORTA clock"]
8pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PORTB` reader - Enable PORTB clock"]
10pub type PortbR = crate::BitReader;
11#[doc = "Field `PORTB` writer - Enable PORTB clock"]
12pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\] clock"]
14pub type Spi0R = crate::BitReader;
15#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\] clock"]
16pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\] clock"]
18pub type Spi1R = crate::BitReader;
19#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\] clock"]
20pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\] clock"]
22pub type Spi2R = crate::BitReader;
23#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\] clock"]
24pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `UART_0` reader - Enable UART\\[0\\] clock"]
26pub type Uart0R = crate::BitReader;
27#[doc = "Field `UART_0` writer - Enable UART\\[0\\] clock"]
28pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `UART_1` reader - Enable UART\\[1\\] clock"]
30pub type Uart1R = crate::BitReader;
31#[doc = "Field `UART_1` writer - Enable UART\\[1\\] clock"]
32pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\] clock"]
34pub type I2c0R = crate::BitReader;
35#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\] clock"]
36pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\] clock"]
38pub type I2c1R = crate::BitReader;
39#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\] clock"]
40pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `IRQSEL` reader - Enable IRQ selector clock"]
42pub type IrqselR = crate::BitReader;
43#[doc = "Field `IRQSEL` writer - Enable IRQ selector clock"]
44pub type IrqselW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `IOCONFIG` reader - Enable IO Configuration block clock"]
46pub type IoconfigR = crate::BitReader;
47#[doc = "Field `IOCONFIG` writer - Enable IO Configuration block clock"]
48pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `UTILITY` reader - Enable utility clock"]
50pub type UtilityR = crate::BitReader;
51#[doc = "Field `UTILITY` writer - Enable utility clock"]
52pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `GPIO` reader - Enable GPIO clock"]
54pub type GpioR = crate::BitReader;
55#[doc = "Field `GPIO` writer - Enable GPIO clock"]
56pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 0 - Enable PORTA clock"]
59 #[inline(always)]
60 pub fn porta(&self) -> PortaR {
61 PortaR::new((self.bits & 1) != 0)
62 }
63 #[doc = "Bit 1 - Enable PORTB clock"]
64 #[inline(always)]
65 pub fn portb(&self) -> PortbR {
66 PortbR::new(((self.bits >> 1) & 1) != 0)
67 }
68 #[doc = "Bit 4 - Enable SPI\\[0\\] clock"]
69 #[inline(always)]
70 pub fn spi_0(&self) -> Spi0R {
71 Spi0R::new(((self.bits >> 4) & 1) != 0)
72 }
73 #[doc = "Bit 5 - Enable SPI\\[1\\] clock"]
74 #[inline(always)]
75 pub fn spi_1(&self) -> Spi1R {
76 Spi1R::new(((self.bits >> 5) & 1) != 0)
77 }
78 #[doc = "Bit 6 - Enable SPI\\[2\\] clock"]
79 #[inline(always)]
80 pub fn spi_2(&self) -> Spi2R {
81 Spi2R::new(((self.bits >> 6) & 1) != 0)
82 }
83 #[doc = "Bit 8 - Enable UART\\[0\\] clock"]
84 #[inline(always)]
85 pub fn uart_0(&self) -> Uart0R {
86 Uart0R::new(((self.bits >> 8) & 1) != 0)
87 }
88 #[doc = "Bit 9 - Enable UART\\[1\\] clock"]
89 #[inline(always)]
90 pub fn uart_1(&self) -> Uart1R {
91 Uart1R::new(((self.bits >> 9) & 1) != 0)
92 }
93 #[doc = "Bit 16 - Enable I2C\\[0\\] clock"]
94 #[inline(always)]
95 pub fn i2c_0(&self) -> I2c0R {
96 I2c0R::new(((self.bits >> 16) & 1) != 0)
97 }
98 #[doc = "Bit 17 - Enable I2C\\[1\\] clock"]
99 #[inline(always)]
100 pub fn i2c_1(&self) -> I2c1R {
101 I2c1R::new(((self.bits >> 17) & 1) != 0)
102 }
103 #[doc = "Bit 21 - Enable IRQ selector clock"]
104 #[inline(always)]
105 pub fn irqsel(&self) -> IrqselR {
106 IrqselR::new(((self.bits >> 21) & 1) != 0)
107 }
108 #[doc = "Bit 22 - Enable IO Configuration block clock"]
109 #[inline(always)]
110 pub fn ioconfig(&self) -> IoconfigR {
111 IoconfigR::new(((self.bits >> 22) & 1) != 0)
112 }
113 #[doc = "Bit 23 - Enable utility clock"]
114 #[inline(always)]
115 pub fn utility(&self) -> UtilityR {
116 UtilityR::new(((self.bits >> 23) & 1) != 0)
117 }
118 #[doc = "Bit 24 - Enable GPIO clock"]
119 #[inline(always)]
120 pub fn gpio(&self) -> GpioR {
121 GpioR::new(((self.bits >> 24) & 1) != 0)
122 }
123}
124impl W {
125 #[doc = "Bit 0 - Enable PORTA clock"]
126 #[inline(always)]
127 pub fn porta(&mut self) -> PortaW<'_, PeripheralClkEnableSpec> {
128 PortaW::new(self, 0)
129 }
130 #[doc = "Bit 1 - Enable PORTB clock"]
131 #[inline(always)]
132 pub fn portb(&mut self) -> PortbW<'_, PeripheralClkEnableSpec> {
133 PortbW::new(self, 1)
134 }
135 #[doc = "Bit 4 - Enable SPI\\[0\\] clock"]
136 #[inline(always)]
137 pub fn spi_0(&mut self) -> Spi0W<'_, PeripheralClkEnableSpec> {
138 Spi0W::new(self, 4)
139 }
140 #[doc = "Bit 5 - Enable SPI\\[1\\] clock"]
141 #[inline(always)]
142 pub fn spi_1(&mut self) -> Spi1W<'_, PeripheralClkEnableSpec> {
143 Spi1W::new(self, 5)
144 }
145 #[doc = "Bit 6 - Enable SPI\\[2\\] clock"]
146 #[inline(always)]
147 pub fn spi_2(&mut self) -> Spi2W<'_, PeripheralClkEnableSpec> {
148 Spi2W::new(self, 6)
149 }
150 #[doc = "Bit 8 - Enable UART\\[0\\] clock"]
151 #[inline(always)]
152 pub fn uart_0(&mut self) -> Uart0W<'_, PeripheralClkEnableSpec> {
153 Uart0W::new(self, 8)
154 }
155 #[doc = "Bit 9 - Enable UART\\[1\\] clock"]
156 #[inline(always)]
157 pub fn uart_1(&mut self) -> Uart1W<'_, PeripheralClkEnableSpec> {
158 Uart1W::new(self, 9)
159 }
160 #[doc = "Bit 16 - Enable I2C\\[0\\] clock"]
161 #[inline(always)]
162 pub fn i2c_0(&mut self) -> I2c0W<'_, PeripheralClkEnableSpec> {
163 I2c0W::new(self, 16)
164 }
165 #[doc = "Bit 17 - Enable I2C\\[1\\] clock"]
166 #[inline(always)]
167 pub fn i2c_1(&mut self) -> I2c1W<'_, PeripheralClkEnableSpec> {
168 I2c1W::new(self, 17)
169 }
170 #[doc = "Bit 21 - Enable IRQ selector clock"]
171 #[inline(always)]
172 pub fn irqsel(&mut self) -> IrqselW<'_, PeripheralClkEnableSpec> {
173 IrqselW::new(self, 21)
174 }
175 #[doc = "Bit 22 - Enable IO Configuration block clock"]
176 #[inline(always)]
177 pub fn ioconfig(&mut self) -> IoconfigW<'_, PeripheralClkEnableSpec> {
178 IoconfigW::new(self, 22)
179 }
180 #[doc = "Bit 23 - Enable utility clock"]
181 #[inline(always)]
182 pub fn utility(&mut self) -> UtilityW<'_, PeripheralClkEnableSpec> {
183 UtilityW::new(self, 23)
184 }
185 #[doc = "Bit 24 - Enable GPIO clock"]
186 #[inline(always)]
187 pub fn gpio(&mut self) -> GpioW<'_, PeripheralClkEnableSpec> {
188 GpioW::new(self, 24)
189 }
190}
191#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
192pub struct PeripheralClkEnableSpec;
193impl crate::RegisterSpec for PeripheralClkEnableSpec {
194 type Ux = u32;
195}
196#[doc = "`read()` method returns [`peripheral_clk_enable::R`](R) reader structure"]
197impl crate::Readable for PeripheralClkEnableSpec {}
198#[doc = "`write(|w| ..)` method takes [`peripheral_clk_enable::W`](W) writer structure"]
199impl crate::Writable for PeripheralClkEnableSpec {
200 type Safety = crate::Unsafe;
201}
202#[doc = "`reset()` method sets PERIPHERAL_CLK_ENABLE to value 0"]
203impl crate::Resettable for PeripheralClkEnableSpec {}