1#[doc = "Register `fcc` reader"]
2pub struct R(crate::R<FCC_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<FCC_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<FCC_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<FCC_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `fcc` writer"]
17pub struct W(crate::W<FCC_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<FCC_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<FCC_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<FCC_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `fifo_depth` reader - "]
38pub type FIFO_DEPTH_R = crate::FieldReader<u32, u32>;
39#[doc = "\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41pub enum RX_FIFO_CLOCK_MODE_A {
42 #[doc = "0: Sync mode, writing/reading clocks use apb clock"]
43 WR_APB = 0,
44 #[doc = "1: Sync mode, writing clock uses apb clock, reading clock uses ahb clock"]
45 W_APB_R_AHB = 1,
46}
47impl From<RX_FIFO_CLOCK_MODE_A> for bool {
48 #[inline(always)]
49 fn from(variant: RX_FIFO_CLOCK_MODE_A) -> Self {
50 variant as u8 != 0
51 }
52}
53#[doc = "Field `rx_fifo_clock_mode` reader - "]
54pub type RX_FIFO_CLOCK_MODE_R = crate::BitReader<RX_FIFO_CLOCK_MODE_A>;
55impl RX_FIFO_CLOCK_MODE_R {
56 #[doc = "Get enumerated values variant"]
57 #[inline(always)]
58 pub fn variant(&self) -> RX_FIFO_CLOCK_MODE_A {
59 match self.bits {
60 false => RX_FIFO_CLOCK_MODE_A::WR_APB,
61 true => RX_FIFO_CLOCK_MODE_A::W_APB_R_AHB,
62 }
63 }
64 #[doc = "Checks if the value of the field is `WR_APB`"]
65 #[inline(always)]
66 pub fn is_wr_apb(&self) -> bool {
67 *self == RX_FIFO_CLOCK_MODE_A::WR_APB
68 }
69 #[doc = "Checks if the value of the field is `W_APB_R_AHB`"]
70 #[inline(always)]
71 pub fn is_w_apb_r_ahb(&self) -> bool {
72 *self == RX_FIFO_CLOCK_MODE_A::W_APB_R_AHB
73 }
74}
75#[doc = "Field `rx_fifo_clock_mode` writer - "]
76pub type RX_FIFO_CLOCK_MODE_W<'a, const O: u8> =
77 crate::BitWriter<'a, u32, FCC_SPEC, RX_FIFO_CLOCK_MODE_A, O>;
78impl<'a, const O: u8> RX_FIFO_CLOCK_MODE_W<'a, O> {
79 #[doc = "Sync mode, writing/reading clocks use apb clock"]
80 #[inline(always)]
81 pub fn wr_apb(self) -> &'a mut W {
82 self.variant(RX_FIFO_CLOCK_MODE_A::WR_APB)
83 }
84 #[doc = "Sync mode, writing clock uses apb clock, reading clock uses ahb clock"]
85 #[inline(always)]
86 pub fn w_apb_r_ahb(self) -> &'a mut W {
87 self.variant(RX_FIFO_CLOCK_MODE_A::W_APB_R_AHB)
88 }
89}
90#[doc = "\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq)]
92pub enum TX_FIFO_CLOCK_ENABLE_A {
93 #[doc = "0: `0`"]
94 DISABLE = 0,
95 #[doc = "1: `1`"]
96 ENABLE = 1,
97}
98impl From<TX_FIFO_CLOCK_ENABLE_A> for bool {
99 #[inline(always)]
100 fn from(variant: TX_FIFO_CLOCK_ENABLE_A) -> Self {
101 variant as u8 != 0
102 }
103}
104#[doc = "Field `tx_fifo_clock_enable` reader - "]
105pub type TX_FIFO_CLOCK_ENABLE_R = crate::BitReader<TX_FIFO_CLOCK_ENABLE_A>;
106impl TX_FIFO_CLOCK_ENABLE_R {
107 #[doc = "Get enumerated values variant"]
108 #[inline(always)]
109 pub fn variant(&self) -> TX_FIFO_CLOCK_ENABLE_A {
110 match self.bits {
111 false => TX_FIFO_CLOCK_ENABLE_A::DISABLE,
112 true => TX_FIFO_CLOCK_ENABLE_A::ENABLE,
113 }
114 }
115 #[doc = "Checks if the value of the field is `DISABLE`"]
116 #[inline(always)]
117 pub fn is_disable(&self) -> bool {
118 *self == TX_FIFO_CLOCK_ENABLE_A::DISABLE
119 }
120 #[doc = "Checks if the value of the field is `ENABLE`"]
121 #[inline(always)]
122 pub fn is_enable(&self) -> bool {
123 *self == TX_FIFO_CLOCK_ENABLE_A::ENABLE
124 }
125}
126#[doc = "Field `tx_fifo_clock_enable` writer - "]
127pub type TX_FIFO_CLOCK_ENABLE_W<'a, const O: u8> =
128 crate::BitWriter<'a, u32, FCC_SPEC, TX_FIFO_CLOCK_ENABLE_A, O>;
129impl<'a, const O: u8> TX_FIFO_CLOCK_ENABLE_W<'a, O> {
130 #[doc = "`0`"]
131 #[inline(always)]
132 pub fn disable(self) -> &'a mut W {
133 self.variant(TX_FIFO_CLOCK_ENABLE_A::DISABLE)
134 }
135 #[doc = "`1`"]
136 #[inline(always)]
137 pub fn enable(self) -> &'a mut W {
138 self.variant(TX_FIFO_CLOCK_ENABLE_A::ENABLE)
139 }
140}
141#[doc = "\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq)]
143pub enum RX_FIFO_CLOCK_ENABLE_A {
144 #[doc = "0: `0`"]
145 DISABLE = 0,
146 #[doc = "1: `1`"]
147 ENABLE = 1,
148}
149impl From<RX_FIFO_CLOCK_ENABLE_A> for bool {
150 #[inline(always)]
151 fn from(variant: RX_FIFO_CLOCK_ENABLE_A) -> Self {
152 variant as u8 != 0
153 }
154}
155#[doc = "Field `rx_fifo_clock_enable` reader - "]
156pub type RX_FIFO_CLOCK_ENABLE_R = crate::BitReader<RX_FIFO_CLOCK_ENABLE_A>;
157impl RX_FIFO_CLOCK_ENABLE_R {
158 #[doc = "Get enumerated values variant"]
159 #[inline(always)]
160 pub fn variant(&self) -> RX_FIFO_CLOCK_ENABLE_A {
161 match self.bits {
162 false => RX_FIFO_CLOCK_ENABLE_A::DISABLE,
163 true => RX_FIFO_CLOCK_ENABLE_A::ENABLE,
164 }
165 }
166 #[doc = "Checks if the value of the field is `DISABLE`"]
167 #[inline(always)]
168 pub fn is_disable(&self) -> bool {
169 *self == RX_FIFO_CLOCK_ENABLE_A::DISABLE
170 }
171 #[doc = "Checks if the value of the field is `ENABLE`"]
172 #[inline(always)]
173 pub fn is_enable(&self) -> bool {
174 *self == RX_FIFO_CLOCK_ENABLE_A::ENABLE
175 }
176}
177#[doc = "Field `rx_fifo_clock_enable` writer - "]
178pub type RX_FIFO_CLOCK_ENABLE_W<'a, const O: u8> =
179 crate::BitWriter<'a, u32, FCC_SPEC, RX_FIFO_CLOCK_ENABLE_A, O>;
180impl<'a, const O: u8> RX_FIFO_CLOCK_ENABLE_W<'a, O> {
181 #[doc = "`0`"]
182 #[inline(always)]
183 pub fn disable(self) -> &'a mut W {
184 self.variant(RX_FIFO_CLOCK_ENABLE_A::DISABLE)
185 }
186 #[doc = "`1`"]
187 #[inline(always)]
188 pub fn enable(self) -> &'a mut W {
189 self.variant(RX_FIFO_CLOCK_ENABLE_A::ENABLE)
190 }
191}
192impl R {
193 #[doc = "Bits 8:31"]
194 #[inline(always)]
195 pub fn fifo_depth(&self) -> FIFO_DEPTH_R {
196 FIFO_DEPTH_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32)
197 }
198 #[doc = "Bit 2"]
199 #[inline(always)]
200 pub fn rx_fifo_clock_mode(&self) -> RX_FIFO_CLOCK_MODE_R {
201 RX_FIFO_CLOCK_MODE_R::new(((self.bits >> 2) & 1) != 0)
202 }
203 #[doc = "Bit 1"]
204 #[inline(always)]
205 pub fn tx_fifo_clock_enable(&self) -> TX_FIFO_CLOCK_ENABLE_R {
206 TX_FIFO_CLOCK_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
207 }
208 #[doc = "Bit 0"]
209 #[inline(always)]
210 pub fn rx_fifo_clock_enable(&self) -> RX_FIFO_CLOCK_ENABLE_R {
211 RX_FIFO_CLOCK_ENABLE_R::new((self.bits & 1) != 0)
212 }
213}
214impl W {
215 #[doc = "Bit 2"]
216 #[inline(always)]
217 pub fn rx_fifo_clock_mode(&mut self) -> RX_FIFO_CLOCK_MODE_W<2> {
218 RX_FIFO_CLOCK_MODE_W::new(self)
219 }
220 #[doc = "Bit 1"]
221 #[inline(always)]
222 pub fn tx_fifo_clock_enable(&mut self) -> TX_FIFO_CLOCK_ENABLE_W<1> {
223 TX_FIFO_CLOCK_ENABLE_W::new(self)
224 }
225 #[doc = "Bit 0"]
226 #[inline(always)]
227 pub fn rx_fifo_clock_enable(&mut self) -> RX_FIFO_CLOCK_ENABLE_W<0> {
228 RX_FIFO_CLOCK_ENABLE_W::new(self)
229 }
230 #[doc = "Writes raw bits to the register."]
231 #[inline(always)]
232 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
233 self.0.bits(bits);
234 self
235 }
236}
237#[doc = "UART FIFO Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcc](index.html) module"]
238pub struct FCC_SPEC;
239impl crate::RegisterSpec for FCC_SPEC {
240 type Ux = u32;
241}
242#[doc = "`read()` method returns [fcc::R](R) reader structure"]
243impl crate::Readable for FCC_SPEC {
244 type Reader = R;
245}
246#[doc = "`write(|w| ..)` method takes [fcc::W](W) writer structure"]
247impl crate::Writable for FCC_SPEC {
248 type Writer = W;
249}
250#[doc = "`reset()` method sets fcc to value 0"]
251impl crate::Resettable for FCC_SPEC {
252 #[inline(always)]
253 fn reset_value() -> Self::Ux {
254 0
255 }
256}