unicorn_engine/
mips.rs

1#![allow(non_camel_case_types)]
2// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
3
4// MIPS registers
5#[repr(C)]
6#[derive(PartialEq, Debug, Clone, Copy)]
7pub enum RegisterMIPS {
8    INVALID = 0,
9
10    // General purpose registers
11    PC = 1,
12    R0 = 2,
13    R1 = 3,
14    R2 = 4,
15    R3 = 5,
16    R4 = 6,
17    R5 = 7,
18    R6 = 8,
19    R7 = 9,
20    R8 = 10,
21    R9 = 11,
22    R10 = 12,
23    R11 = 13,
24    R12 = 14,
25    R13 = 15,
26    R14 = 16,
27    R15 = 17,
28    R16 = 18,
29    R17 = 19,
30    R18 = 20,
31    R19 = 21,
32    R20 = 22,
33    R21 = 23,
34    R22 = 24,
35    R23 = 25,
36    R24 = 26,
37    R25 = 27,
38    R26 = 28,
39    R27 = 29,
40    R28 = 30,
41    R29 = 31,
42    R30 = 32,
43    R31 = 33,
44
45    // DSP registers
46    DSPCCOND = 34,
47    DSPCARRY = 35,
48    DSPEFI = 36,
49    DSPOUTFLAG = 37,
50    DSPOUTFLAG16_19 = 38,
51    DSPOUTFLAG20 = 39,
52    DSPOUTFLAG21 = 40,
53    DSPOUTFLAG22 = 41,
54    DSPOUTFLAG23 = 42,
55    DSPPOS = 43,
56    DSPSCOUNT = 44,
57
58    // ACC registers
59    AC0 = 45,
60    AC1 = 46,
61    AC2 = 47,
62    AC3 = 48,
63
64    // COP registers
65    CC0 = 49,
66    CC1 = 50,
67    CC2 = 51,
68    CC3 = 52,
69    CC4 = 53,
70    CC5 = 54,
71    CC6 = 55,
72    CC7 = 56,
73
74    // FPU registers
75    F0 = 57,
76    F1 = 58,
77    F2 = 59,
78    F3 = 60,
79    F4 = 61,
80    F5 = 62,
81    F6 = 63,
82    F7 = 64,
83    F8 = 65,
84    F9 = 66,
85    F10 = 67,
86    F11 = 68,
87    F12 = 69,
88    F13 = 70,
89    F14 = 71,
90    F15 = 72,
91    F16 = 73,
92    F17 = 74,
93    F18 = 75,
94    F19 = 76,
95    F20 = 77,
96    F21 = 78,
97    F22 = 79,
98    F23 = 80,
99    F24 = 81,
100    F25 = 82,
101    F26 = 83,
102    F27 = 84,
103    F28 = 85,
104    F29 = 86,
105    F30 = 87,
106    F31 = 88,
107    FCC0 = 89,
108    FCC1 = 90,
109    FCC2 = 91,
110    FCC3 = 92,
111    FCC4 = 93,
112    FCC5 = 94,
113    FCC6 = 95,
114    FCC7 = 96,
115
116    // AFPR128
117    W0 = 97,
118    W1 = 98,
119    W2 = 99,
120    W3 = 100,
121    W4 = 101,
122    W5 = 102,
123    W6 = 103,
124    W7 = 104,
125    W8 = 105,
126    W9 = 106,
127    W10 = 107,
128    W11 = 108,
129    W12 = 109,
130    W13 = 110,
131    W14 = 111,
132    W15 = 112,
133    W16 = 113,
134    W17 = 114,
135    W18 = 115,
136    W19 = 116,
137    W20 = 117,
138    W21 = 118,
139    W22 = 119,
140    W23 = 120,
141    W24 = 121,
142    W25 = 122,
143    W26 = 123,
144    W27 = 124,
145    W28 = 125,
146    W29 = 126,
147    W30 = 127,
148    W31 = 128,
149    HI = 129,
150    LO = 130,
151    P0 = 131,
152    P1 = 132,
153    P2 = 133,
154    MPL0 = 134,
155    MPL1 = 135,
156    MPL2 = 136,
157    CP0_CONFIG3 = 137,
158    CP0_USERLOCAL = 138,
159    CP0_STATUS = 139,
160    ENDING = 140,
161}
162
163impl RegisterMIPS {
164    // alias registers
165    // (assoc) ZERO = 2,
166    // (assoc) AT = 3,
167    // (assoc) V0 = 4,
168    // (assoc) V1 = 5,
169    // (assoc) A0 = 6,
170    // (assoc) A1 = 7,
171    // (assoc) A2 = 8,
172    // (assoc) A3 = 9,
173    // (assoc) T0 = 10,
174    // (assoc) T1 = 11,
175    // (assoc) T2 = 12,
176    // (assoc) T3 = 13,
177    // (assoc) T4 = 14,
178    // (assoc) T5 = 15,
179    // (assoc) T6 = 16,
180    // (assoc) T7 = 17,
181    // (assoc) S0 = 18,
182    // (assoc) S1 = 19,
183    // (assoc) S2 = 20,
184    // (assoc) S3 = 21,
185    // (assoc) S4 = 22,
186    // (assoc) S5 = 23,
187    // (assoc) S6 = 24,
188    // (assoc) S7 = 25,
189    // (assoc) T8 = 26,
190    // (assoc) T9 = 27,
191    // (assoc) K0 = 28,
192    // (assoc) K1 = 29,
193    // (assoc) GP = 30,
194    // (assoc) SP = 31,
195    // (assoc) FP = 32,
196    // (assoc) S8 = 32,
197    // (assoc) RA = 33,
198    // (assoc) HI0 = 45,
199    // (assoc) HI1 = 46,
200    // (assoc) HI2 = 47,
201    // (assoc) HI3 = 48,
202    // (assoc) LO0 = 45,
203    // (assoc) LO1 = 46,
204    // (assoc) LO2 = 47,
205    // (assoc) LO3 = 48,
206    pub const ZERO: RegisterMIPS = RegisterMIPS::R0;
207    pub const AT: RegisterMIPS = RegisterMIPS::R1;
208    pub const V0: RegisterMIPS = RegisterMIPS::R2;
209    pub const V1: RegisterMIPS = RegisterMIPS::R3;
210    pub const A0: RegisterMIPS = RegisterMIPS::R4;
211    pub const A1: RegisterMIPS = RegisterMIPS::R5;
212    pub const A2: RegisterMIPS = RegisterMIPS::R6;
213    pub const A3: RegisterMIPS = RegisterMIPS::R7;
214    pub const T0: RegisterMIPS = RegisterMIPS::R8;
215    pub const T1: RegisterMIPS = RegisterMIPS::R9;
216    pub const T2: RegisterMIPS = RegisterMIPS::R10;
217    pub const T3: RegisterMIPS = RegisterMIPS::R11;
218    pub const T4: RegisterMIPS = RegisterMIPS::R12;
219    pub const T5: RegisterMIPS = RegisterMIPS::R13;
220    pub const T6: RegisterMIPS = RegisterMIPS::R14;
221    pub const T7: RegisterMIPS = RegisterMIPS::R15;
222    pub const S0: RegisterMIPS = RegisterMIPS::R16;
223    pub const S1: RegisterMIPS = RegisterMIPS::R17;
224    pub const S2: RegisterMIPS = RegisterMIPS::R18;
225    pub const S3: RegisterMIPS = RegisterMIPS::R19;
226    pub const S4: RegisterMIPS = RegisterMIPS::R20;
227    pub const S5: RegisterMIPS = RegisterMIPS::R21;
228    pub const S6: RegisterMIPS = RegisterMIPS::R22;
229    pub const S7: RegisterMIPS = RegisterMIPS::R23;
230    pub const T8: RegisterMIPS = RegisterMIPS::R24;
231    pub const T9: RegisterMIPS = RegisterMIPS::R25;
232    pub const K0: RegisterMIPS = RegisterMIPS::R26;
233    pub const K1: RegisterMIPS = RegisterMIPS::R27;
234    pub const GP: RegisterMIPS = RegisterMIPS::R28;
235    pub const SP: RegisterMIPS = RegisterMIPS::R29;
236    pub const FP: RegisterMIPS = RegisterMIPS::R30;
237    pub const S8: RegisterMIPS = RegisterMIPS::R30;
238    pub const RA: RegisterMIPS = RegisterMIPS::R31;
239    pub const HI0: RegisterMIPS = RegisterMIPS::AC0;
240    pub const HI1: RegisterMIPS = RegisterMIPS::AC1;
241    pub const HI2: RegisterMIPS = RegisterMIPS::AC2;
242    pub const HI3: RegisterMIPS = RegisterMIPS::AC3;
243    pub const LO0: RegisterMIPS = RegisterMIPS::AC0;
244    pub const LO1: RegisterMIPS = RegisterMIPS::AC1;
245    pub const LO2: RegisterMIPS = RegisterMIPS::AC2;
246    pub const LO3: RegisterMIPS = RegisterMIPS::AC3;
247}
248
249impl From<RegisterMIPS> for i32 {
250    fn from(r: RegisterMIPS) -> Self {
251        r as i32
252    }
253}
254
255#[repr(i32)]
256#[derive(Debug, Copy, Clone, PartialEq, Eq)]
257pub enum Mips32CpuModel {
258    UC_CPU_MIPS32_4KC = 0,
259    UC_CPU_MIPS32_4KM = 1,
260    UC_CPU_MIPS32_4KECR1 = 2,
261    UC_CPU_MIPS32_4KEMR1 = 3,
262    UC_CPU_MIPS32_4KEC = 4,
263    UC_CPU_MIPS32_4KEM = 5,
264    UC_CPU_MIPS32_24KC = 6,
265    UC_CPU_MIPS32_24KEC = 7,
266    UC_CPU_MIPS32_24KF = 8,
267    UC_CPU_MIPS32_34KF = 9,
268    UC_CPU_MIPS32_74KF = 10,
269    UC_CPU_MIPS32_M14K = 11,
270    UC_CPU_MIPS32_M14KC = 12,
271    UC_CPU_MIPS32_P5600 = 13,
272    UC_CPU_MIPS32_MIPS32R6_GENERIC = 14,
273    UC_CPU_MIPS32_I7200 = 15,
274}
275
276impl From<Mips32CpuModel> for i32 {
277    fn from(value: Mips32CpuModel) -> Self {
278        value as i32
279    }
280}
281
282impl From<&Mips32CpuModel> for i32 {
283    fn from(value: &Mips32CpuModel) -> Self {
284        *value as i32
285    }
286}
unicorn_engine/mips.rs

unicorn_engine/
mips.rs
