unicorn_engine/
arm64.rs

1#![allow(non_camel_case_types)]
2
3// ARM64 registers
4#[repr(C)]
5#[derive(PartialEq, Debug, Clone, Copy)]
6pub enum RegisterARM64 {
7    INVALID = 0,
8    X29 = 1,
9    X30 = 2,
10    NZCV = 3,
11    SP = 4,
12    WSP = 5,
13    WZR = 6,
14    XZR = 7,
15    B0 = 8,
16    B1 = 9,
17    B2 = 10,
18    B3 = 11,
19    B4 = 12,
20    B5 = 13,
21    B6 = 14,
22    B7 = 15,
23    B8 = 16,
24    B9 = 17,
25    B10 = 18,
26    B11 = 19,
27    B12 = 20,
28    B13 = 21,
29    B14 = 22,
30    B15 = 23,
31    B16 = 24,
32    B17 = 25,
33    B18 = 26,
34    B19 = 27,
35    B20 = 28,
36    B21 = 29,
37    B22 = 30,
38    B23 = 31,
39    B24 = 32,
40    B25 = 33,
41    B26 = 34,
42    B27 = 35,
43    B28 = 36,
44    B29 = 37,
45    B30 = 38,
46    B31 = 39,
47    D0 = 40,
48    D1 = 41,
49    D2 = 42,
50    D3 = 43,
51    D4 = 44,
52    D5 = 45,
53    D6 = 46,
54    D7 = 47,
55    D8 = 48,
56    D9 = 49,
57    D10 = 50,
58    D11 = 51,
59    D12 = 52,
60    D13 = 53,
61    D14 = 54,
62    D15 = 55,
63    D16 = 56,
64    D17 = 57,
65    D18 = 58,
66    D19 = 59,
67    D20 = 60,
68    D21 = 61,
69    D22 = 62,
70    D23 = 63,
71    D24 = 64,
72    D25 = 65,
73    D26 = 66,
74    D27 = 67,
75    D28 = 68,
76    D29 = 69,
77    D30 = 70,
78    D31 = 71,
79    H0 = 72,
80    H1 = 73,
81    H2 = 74,
82    H3 = 75,
83    H4 = 76,
84    H5 = 77,
85    H6 = 78,
86    H7 = 79,
87    H8 = 80,
88    H9 = 81,
89    H10 = 82,
90    H11 = 83,
91    H12 = 84,
92    H13 = 85,
93    H14 = 86,
94    H15 = 87,
95    H16 = 88,
96    H17 = 89,
97    H18 = 90,
98    H19 = 91,
99    H20 = 92,
100    H21 = 93,
101    H22 = 94,
102    H23 = 95,
103    H24 = 96,
104    H25 = 97,
105    H26 = 98,
106    H27 = 99,
107    H28 = 100,
108    H29 = 101,
109    H30 = 102,
110    H31 = 103,
111    Q0 = 104,
112    Q1 = 105,
113    Q2 = 106,
114    Q3 = 107,
115    Q4 = 108,
116    Q5 = 109,
117    Q6 = 110,
118    Q7 = 111,
119    Q8 = 112,
120    Q9 = 113,
121    Q10 = 114,
122    Q11 = 115,
123    Q12 = 116,
124    Q13 = 117,
125    Q14 = 118,
126    Q15 = 119,
127    Q16 = 120,
128    Q17 = 121,
129    Q18 = 122,
130    Q19 = 123,
131    Q20 = 124,
132    Q21 = 125,
133    Q22 = 126,
134    Q23 = 127,
135    Q24 = 128,
136    Q25 = 129,
137    Q26 = 130,
138    Q27 = 131,
139    Q28 = 132,
140    Q29 = 133,
141    Q30 = 134,
142    Q31 = 135,
143    S0 = 136,
144    S1 = 137,
145    S2 = 138,
146    S3 = 139,
147    S4 = 140,
148    S5 = 141,
149    S6 = 142,
150    S7 = 143,
151    S8 = 144,
152    S9 = 145,
153    S10 = 146,
154    S11 = 147,
155    S12 = 148,
156    S13 = 149,
157    S14 = 150,
158    S15 = 151,
159    S16 = 152,
160    S17 = 153,
161    S18 = 154,
162    S19 = 155,
163    S20 = 156,
164    S21 = 157,
165    S22 = 158,
166    S23 = 159,
167    S24 = 160,
168    S25 = 161,
169    S26 = 162,
170    S27 = 163,
171    S28 = 164,
172    S29 = 165,
173    S30 = 166,
174    S31 = 167,
175    W0 = 168,
176    W1 = 169,
177    W2 = 170,
178    W3 = 171,
179    W4 = 172,
180    W5 = 173,
181    W6 = 174,
182    W7 = 175,
183    W8 = 176,
184    W9 = 177,
185    W10 = 178,
186    W11 = 179,
187    W12 = 180,
188    W13 = 181,
189    W14 = 182,
190    W15 = 183,
191    W16 = 184,
192    W17 = 185,
193    W18 = 186,
194    W19 = 187,
195    W20 = 188,
196    W21 = 189,
197    W22 = 190,
198    W23 = 191,
199    W24 = 192,
200    W25 = 193,
201    W26 = 194,
202    W27 = 195,
203    W28 = 196,
204    W29 = 197,
205    W30 = 198,
206    X0 = 199,
207    X1 = 200,
208    X2 = 201,
209    X3 = 202,
210    X4 = 203,
211    X5 = 204,
212    X6 = 205,
213    X7 = 206,
214    X8 = 207,
215    X9 = 208,
216    X10 = 209,
217    X11 = 210,
218    X12 = 211,
219    X13 = 212,
220    X14 = 213,
221    X15 = 214,
222    X16 = 215,
223    X17 = 216,
224    X18 = 217,
225    X19 = 218,
226    X20 = 219,
227    X21 = 220,
228    X22 = 221,
229    X23 = 222,
230    X24 = 223,
231    X25 = 224,
232    X26 = 225,
233    X27 = 226,
234    X28 = 227,
235    V0 = 228,
236    V1 = 229,
237    V2 = 230,
238    V3 = 231,
239    V4 = 232,
240    V5 = 233,
241    V6 = 234,
242    V7 = 235,
243    V8 = 236,
244    V9 = 237,
245    V10 = 238,
246    V11 = 239,
247    V12 = 240,
248    V13 = 241,
249    V14 = 242,
250    V15 = 243,
251    V16 = 244,
252    V17 = 245,
253    V18 = 246,
254    V19 = 247,
255    V20 = 248,
256    V21 = 249,
257    V22 = 250,
258    V23 = 251,
259    V24 = 252,
260    V25 = 253,
261    V26 = 254,
262    V27 = 255,
263    V28 = 256,
264    V29 = 257,
265    V30 = 258,
266    V31 = 259,
267
268    // pseudo registers
269    PC = 260,
270    CPACR_EL1 = 261,
271
272    // thread registers, depreciated, use CP_REG instead
273    TPIDR_EL0 = 262,
274    TPIDRRO_EL0 = 263,
275    TPIDR_EL1 = 264,
276    PSTATE = 265,
277
278    // exception link registers, depreciated, use CP_REG instead
279    ELR_EL0 = 266,
280    ELR_EL1 = 267,
281    ELR_EL2 = 268,
282    ELR_EL3 = 269,
283
284    // stack pointers registers, depreciated, use CP_REG instead
285    SP_EL0 = 270,
286    SP_EL1 = 271,
287    SP_EL2 = 272,
288    SP_EL3 = 273,
289
290    // other CP15 registers, depreciated, use CP_REG instead
291    TTBR0_EL1 = 274,
292    TTBR1_EL1 = 275,
293    ESR_EL0 = 276,
294    ESR_EL1 = 277,
295    ESR_EL2 = 278,
296    ESR_EL3 = 279,
297    FAR_EL0 = 280,
298    FAR_EL1 = 281,
299    FAR_EL2 = 282,
300    FAR_EL3 = 283,
301    PAR_EL1 = 284,
302    MAIR_EL1 = 285,
303    VBAR_EL0 = 286,
304    VBAR_EL1 = 287,
305    VBAR_EL2 = 288,
306    VBAR_EL3 = 289,
307    CP_REG = 290,
308    ENDING = 291,
309}
310
311impl RegisterARM64 {
312    // alias registers
313    // (assoc) IP0 = 215,
314    // (assoc) IP1 = 216,
315    // (assoc) FP = 1,
316    // (assoc) LR = 2,
317    pub const IP0: RegisterARM64 = RegisterARM64::X16;
318    pub const IP1: RegisterARM64 = RegisterARM64::X17;
319    pub const FP: RegisterARM64 = RegisterARM64::X29;
320    pub const LR: RegisterARM64 = RegisterARM64::X30;
321}
322
323impl From<RegisterARM64> for i32 {
324    fn from(r: RegisterARM64) -> Self {
325        r as i32
326    }
327}
328
329#[repr(i32)]
330#[derive(Debug, Copy, Clone, PartialEq, Eq)]
331pub enum Arm64CpuModel {
332    UC_CPU_ARM64_A57 = 0,
333    UC_CPU_ARM64_A53 = 1,
334    UC_CPU_ARM64_A72 = 2,
335    UC_CPU_ARM64_MAX = 3,
336}
337
338impl From<Arm64CpuModel> for i32 {
339    fn from(value: Arm64CpuModel) -> Self {
340        value as i32
341    }
342}
343
344impl From<&Arm64CpuModel> for i32 {
345    fn from(value: &Arm64CpuModel) -> Self {
346        (*value) as i32
347    }
348}
unicorn_engine/arm64.rs

unicorn_engine/
arm64.rs
