ull65/
access.rs

1use ull::{Bus, Byte, Word};
2
3/// Phase within a bus cycle. Some hardware (e.g., NES DMA) cares whether we're in
4/// the read (GET) or write (PUT) half of a cycle.
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Phase {
7    Read,
8    Write,
9}
10
11/// High-level purpose of a bus access combined with its direction (6502-specific).
12#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
13pub enum AccessType {
14    #[default]
15    DataRead,
16    DataWrite,
17    OpcodeFetch,
18    StackRead,
19    StackWrite,
20    InterruptVectorRead,
21    DmaRead,
22    DmaWrite,
23    DummyRead,
24}
25
26impl AccessType {
27    #[must_use]
28    pub const fn is_write(self) -> bool {
29        matches!(
30            self,
31            AccessType::DataWrite | AccessType::StackWrite | AccessType::DmaWrite
32        )
33    }
34
35    #[must_use]
36    pub const fn phase(self) -> Phase {
37        if self.is_write() {
38            Phase::Write
39        } else {
40            Phase::Read
41        }
42    }
43}
44
45pub trait ResetVectorExt {
46    fn set_reset_vector(&mut self, target: Word);
47}
48
49impl<B> ResetVectorExt for B
50where
51    B: Bus<Access = AccessType, Data = Byte>,
52{
53    fn set_reset_vector(&mut self, target: Word) {
54        self.write(Word(0xFFFC), target.lo(), AccessType::DataWrite);
55        self.write(Word(0xFFFD), target.hi(), AccessType::DataWrite);
56    }
57}
ull65/access.rs

ull65/
access.rs
