Struct uart8250::uart::MmioUart8250[][src]

pub struct MmioUart8250<const BASE: usize>;
Expand description

MMIO version of uart 8250

Noticed This is only tested on the NS16550 compatible UART used in QEMU 5.0 virt machine of RISC-V


A basic way to init the uart with interrupt enable

Other way to init can be done by using other methods below

Read a byte from uart

Return None when data is not ready (RBR[0] != 1)

Write a byte to uart

Error are not concerned now MAYBE TODO

write THR (offset + 0)

Write Transmitter Holding Buffer to send data

Transmitter Holding Buffer/Receiver Buffer

Offset: +0 . The Transmit and Receive buffers are related, and often even use the very same memory. This is also one of the areas where later versions of the 8250 chip have a significant impact, as the later models incorporate some internal buffering of the data within the chip before it gets transmitted as serial data. The base 8250 chip can only receive one byte at a time, while later chips like the 16550 chip will hold up to 16 bytes either to transmit or to receive (sometimes both… depending on the manufacturer) before you have to wait for the character to be sent. This can be useful in multi-tasking environments where you have a computer doing many things, and it may be a couple of milliseconds before you get back to dealing with serial data flow.

These registers really are the “heart” of serial data communication, and how data is transferred from your software to another computer and how it gets data from other devices. Reading and Writing to these registers is simply a matter of accessing the Port I/O address for the respective UART.

If the receive buffer is occupied or the FIFO is full, the incoming data is discarded and the Receiver Line Status interrupt is written to the IIR register. The Overrun Error bit is also set in the Line Status Register.

read RBR (offset + 0)

Read Receiver Buffer to get data

read DLL (offset + 0)

get divisor latch low byte in the register

Divisor Latch Bytes

Offset: +0 and +1 . The Divisor Latch Bytes are what control the baud rate of the modem. As you might guess from the name of this register, it is used as a divisor to determine what baud rate that the chip is going to be transmitting at.

Used clock 1.8432 MHz as example, first divide 16 and get 115200. Then use the formula to get divisor latch value:

DivisorLatchValue = 115200 / BaudRate

This gives the following table:

Baud RateDivisor (in decimal)Divisor Latch High ByteDivisor Latch Low Byte

write DLL (offset + 0)

set divisor latch low byte in the register

read DLH (offset + 1)

get divisor latch high byte in the register

write DLH (offset + 1)

set divisor latch high byte in the register

Read IER (offset + 1)

Read IER to get what interrupts are enabled

Interrupt Enable Register

Offset: +1 . This register allows you to control when and how the UART is going to trigger an interrupt event with the hardware interrupt associated with the serial COM port. If used properly, this can enable an efficient use of system resources and allow you to react to information being sent across a serial data line in essentially real-time conditions. Some more on that will be covered later, but the point here is that you can use the UART to let you know exactly when you need to extract some data. This register has both read- and write-access.

The following is a table showing each bit in this register and what events that it will enable to allow you check on the status of this chip:

5Enables Low Power Mode (16750)
4Enables Sleep Mode (16750)
3Enable Modem Status Interrupt
2Enable Receiver Line Status Interrupt
1Enable Transmitter Holding Register Empty Interrupt
0Enable Received Data Available Interrupt

Write IER (offset + 1)

Write Interrupt Enable Register to turn on/off interrupts

get whether low power mode (16750) is enabled (IER[5])

toggle low power mode (16750) (IER[5])

get whether sleep mode (16750) is enabled (IER[4])

toggle sleep mode (16750) (IER[4])

get whether modem status interrupt is enabled (IER[3])

toggle modem status interrupt (IER[3])

get whether receiver line status interrupt is enabled (IER[2])

toggle receiver line status interrupt (IER[2])

get whether transmitter holding register empty interrupt is enabled (IER[1])

toggle transmitter holding register empty interrupt (IER[1])

get whether received data available is enabled (IER[0])

toggle received data available (IER[0])

Read IIR (offset + 2)

Interrupt Identification Register

Offset: +2 . This register is to be used to help identify what the unique characteristics of the UART chip that you are using has. This chip has two uses:

  • Identification of why the UART triggered an interrupt.
  • Identification of the UART chip itself.

Of these, identification of why the interrupt service routine has been invoked is perhaps the most important.

The following table explains some of the details of this register, and what each bit on it represents:

7 and 6Bit 7Bit 6
00No FIFO on chip
01Reserved condition
10FIFO enabled, but not functioning
11FIFO enabled
564 Byte FIFO Enabled (16750 only)
3, 2 and 1Bit 3Bit 2Bit 1Reset Method
000Modem Status InterruptReading Modem Status Register(MSR)
001Transmitter Holding Register Empty InterruptReading Interrupt Identification Register(IIR) or Writing to Transmit Holding Buffer(THR)
010Received Data Available InterruptReading Receive Buffer Register(RBR)
011Receiver Line Status InterruptReading Line Status Register(LSR)
110Time-out Interrupt Pending (16550 & later)Reading Receive Buffer Register(RBR)
0Interrupt Pending Flag

Read IIR[7:6] to get FIFO status

get whether 64 Byte fifo (16750 only) is enabled (IIR[5])

Read IIR[3:1] to get interrupt type

get whether interrupt is pending (IIR[0])

Write FCR (offset + 2) to control FIFO buffers

FIFO Control Register

Offset: +2 . This is a relatively “new” register that was not a part of the original 8250 UART implementation. The purpose of this register is to control how the First In/First Out (FIFO) buffers will behave on the chip and to help you fine-tune their performance in your application. This even gives you the ability to “turn on” or “turn off” the FIFO.

Keep in mind that this is a “write only” register. Attempting to read in the contents will only give you the Interrupt Identification Register (IIR), which has a totally different context.

7 & 6Bit 7Bit 6Interrupt Trigger Level (16 byte)Trigger Level (64 byte)
001 Byte1 Byte
014 Bytes16 Bytes
108 Bytes32 Bytes
1114 Bytes56 Bytes
5Enable 64 Byte FIFO (16750)
3DMA Mode Select
2Clear Transmit FIFO
1Clear Receive FIFO
0Enable FIFOs

Read LCR (offset + 3)

Read Line Control Register to get the data protocol and DLAB

Line Control Register

Offset: +3 . This register has two major purposes:

  • Setting the Divisor Latch Access Bit (DLAB), allowing you to set the values of the Divisor Latch Bytes.
  • Setting the bit patterns that will be used for both receiving and transmitting the serial data. In other words, the serial data protocol you will be using (8-1-None, 5-2-Even, etc.).
7Divisor Latch Access Bit
6Set Break Enable
3, 4 & 5Bit 5Bit 4Bit 3Parity Select
000No Parity
001Odd Parity
011Even Parity
20One Stop Bit
11.5 Stop Bits or 2 Stop Bits
0 & 1Bit 1Bit 0Word Length
005 Bits
016 Bits
107 Bits
118 Bits

Write LCR (offset + 3)

Write Line Control Register to set DLAB and the serial data protocol

get whether DLAB is enabled

toggle DLAB

get parity of used data protocol

set parity

get stop bit of used data protocol

Simply return a u8 to indicate 1 or 1.5/2 bits

set stop bit, only 1 and 2 can be used as stop_bit

get word length of used data protocol

set word length, only 5..=8 can be used as length

Read MCR (offset + 4)

Read Modem Control Register to get how flow is controlled

Modem Control Register

Offset: +4 . This register allows you to do “hardware” flow control, under software control. Or in a more practical manner, it allows direct manipulation of four different wires on the UART that you can set to any series of independent logical states, and be able to offer control of the modem. It should also be noted that most UARTs need Auxiliary Output 2 set to a logical “1” to enable interrupts.

5Autoflow Control Enabled (16750)
4Loopback Mode
3Auxiliary Output 2
2Auxiliary Output 1
1Request To Send
0Data Terminal Ready

Write MCR (offset + 4)

Write Modem Control Register to control flow

Read LSR (offset + 5)

Line Status Register

Offset: +5 . This register is used primarily to give you information on possible error conditions that may exist within the UART, based on the data that has been received. Keep in mind that this is a “read only” register, and any data written to this register is likely to be ignored or worse, cause different behavior in the UART. There are several uses for this information, and some information will be given below on how it can be useful for diagnosing problems with your serial data connection:

7Error in Received FIFO
6Empty Data Holding Registers
5Empty Transmitter Holding Register
4Break Interrupt
3Framing Error
2Parity Error
1Overrun Error
0Data Ready

Read MSR (offset + 6)

Modem Status Register

Offset: +6 . This register is another read-only register that is here to inform your software about the current status of the modem. The modem accessed in this manner can either be an external modem, or an internal modem that uses a UART as an interface to the computer.

7Carrier Detect
6Ring Indicator
5Data Set Ready
4Clear To Send
3Delta Data Carrier Detect
2Trailing Edge Ring Indicator
1Delta Data Set Ready
0Delta Clear To Send

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