Crate turbografx 

A TurboGrafx-16 / PC Engine emulator core.

The console is built around the Hudson Soft / NEC HuC6280 CPU (a 65C02 derivative with an integrated MMU, PSG, timer and I/O port) talking to two video chips:

• HuC6270 VDC — the Video Display Controller. This is the “graphics processor”: it owns 64 KiB of VRAM and produces the tile/sprite picture. It lives in vdc and is the part you’ll be fleshing out next.
• HuC6260 VCE — the Video Color Encoder. It holds the 512-entry color palette and the dot-clock selection. It lives in vce.

How the pieces fit together

           +-----------------------------------------------+
           |                    Console                    |
           |                                               |
  CPU  <-->|  mos6502::CPU<SystemBus, Huc6280>             |
           |        |                                      |
           |        v   (Bus trait: get_byte/set_byte)     |
           |   SystemBus  -- MMU (MPR0-7) + memory map     |
           |     |   |   |        |        |       |       |
           |    ROM RAM VDC      VCE     Timer    IRQ ctl  |
           +-----------------------------------------------+

The CPU only ever emits 16-bit logical addresses. The SystemBus performs the HuC6280 MMU translation (logical → 21-bit physical) using a shadow copy of the mapping registers, then dispatches to ROM, work RAM or the hardware page (bank $FF).

See crate::bus for the important note on interrupt-vector handling.

Re-exports

pub use bus::SystemBus;

pub use cartridge::Cartridge;

pub use console::Console;

Modules

bus

The HuC6280 system bus: MMU translation + the PC Engine memory map.

cartridge

HuCard (cartridge) ROM handling.

console

The assembled console: CPU + system bus, with a frame-stepping loop.

interrupts

HuC6280 interrupt controller (hardware page $FF, offset $1400..=$17FF).

io

Joypad / I/O port (hardware page $FF, offset $1000..=$13FF).

psg

PSG — the 6-channel programmable sound generator built into the HuC6280 (hardware page $FF, offset $0800..=$0BFF).

timer

HuC6280 programmable timer (hardware page $FF, offset $0C00..=$0FFF).

vce

HuC6260 VCE — Video Color Encoder (hardware page $FF, offset $0400..=$07FF).

vdc

HuC6270 VDC — Video Display Controller (hardware page $FF, offset $0000..=$03FF).

Constants

ACTIVE_CYCLES_PER_SCANLINE

Approximate CPU cycles of the active-display portion of a scanline (before HBlank). The remainder, CPU_CYCLES_PER_SCANLINE - ACTIVE_CYCLES_PER_SCANLINE, is HBlank, during which raster/vblank interrupt handlers run and program the registers for the next line.

CPU_CLOCK_HZ

CPU clock in its high-speed mode: 21.477 MHz master / 3 ≈ 7.16 MHz.

CPU_CYCLES_PER_SCANLINE

Approximate CPU cycles per scanline at 7.16 MHz.

SCANLINES_PER_FRAME

NTSC scanlines per frame (262 active + retrace ≈ 262/263).