Expand description
Memory layout optimizations for improved cache performance.
This module provides data structures and algorithms optimized for cache-friendly memory layouts, reducing memory bandwidth usage and improving performance through better spatial and temporal locality.
§Key Optimizations
- Structure of Arrays (SoA): Better vectorization and cache usage
- Memory Alignment: Ensure data aligns to cache line boundaries
- Hot/Cold Data Separation: Keep frequently accessed data together
- Prefetch-Friendly Layouts: Optimize for hardware prefetchers
- NUMA-Aware Allocation: Optimize for multi-socket systems
Structs§
- Aligned
Allocator - Aligned memory allocator for cache-friendly data structures.
- Alignment
Config - Memory alignment configuration for optimal cache performance.
- Layout
Optimized Adam - Memory-optimized Adam optimizer using SoA layout.
- Layout
Stats - Memory layout optimization statistics.
- Parameter
Info - Information about a parameter in SoA layout.
- SoAOptimizer
State - Structure of Arrays (SoA) layout for optimizer state.