Crate trit_vsa 

Balanced ternary arithmetic library with bitsliced storage and VSA operations.

This crate provides efficient representations and operations for balanced ternary values {-1, 0, +1}. It supports both dense (bitsliced) and sparse storage formats, along with Vector Symbolic Architecture (VSA) operations for hyperdimensional computing.

Features

• Core Types: Trit, Tryte3 (3 trits), Word6 (6 trits)
• Vector Storage: PackedTritVec (bitsliced), SparseVec (COO format)
• VSA Operations: Bundle (majority), Bind (XOR-like), Similarity
• SIMD: Optional AVX2/NEON acceleration with the simd feature

Quick Start

use trit_vsa::{Trit, PackedTritVec, vsa};

// Create a ternary vector
let mut vec = PackedTritVec::new(1000);
vec.set(0, Trit::P);   // +1
vec.set(1, Trit::N);   // -1
vec.set(2, Trit::Z);   // 0

// Compute dot product
let other = PackedTritVec::new(1000);
let dot = vec.dot(&other);

// VSA operations
let bundled = vsa::bundle(&vec, &other);
let similarity = vsa::cosine_similarity(&vec, &other);

Representation

Ternary values are stored using a bitsliced representation with two planes:

Value | +plane | -plane
------+--------+-------
  +1  |   1    |   0
   0  |   0    |   0
  -1  |   0    |   1

This enables efficient popcount-based operations like dot products.

Feature Flags

• default: No additional features
• simd: Enable AVX2/NEON SIMD optimizations
• cuda: Enable GPU acceleration via CubeCL

Re-exports

pub use dispatch::DevicePreference;

pub use dispatch::DispatchConfig;

pub use dispatch::Format;

pub use dispatch::Operation;

pub use dispatch::TritVector;

pub use kernels::get_backend;

pub use kernels::get_backend_for_size;

pub use kernels::BackendConfig;

pub use kernels::BackendPreference;

pub use kernels::CpuBackend;

pub use kernels::DynamicBackend;

pub use kernels::RandomConfig;

pub use kernels::TernaryBackend;

Modules

arithmetic

Balanced ternary arithmetic utilities.

dispatch

Smart kernel dispatch for optimal ternary operations.

kernels

Modular kernel architecture for ternary VSA operations.

prelude

Prelude module for convenient imports.

simd

SIMD-optimized operations for ternary vectors.

vsa

Vector Symbolic Architecture (VSA) operations for ternary vectors.

Structs

PackedTritVec

A packed ternary vector using bitsliced storage.

SparseVec

A sparse ternary vector using COO (Coordinate) format.

Tryte3

A balanced ternary byte consisting of 3 trits.

Word6

A balanced ternary word consisting of 6 trits.

Enums

TernaryError

Errors that can occur during ternary operations.

Trit

A balanced ternary digit (trit) with values {-1, 0, +1}.

Constants

TRYTE3_MAX

Maximum value representable by a Tryte3 (+13).

TRYTE3_MIN

Minimum value representable by a Tryte3 (-13).

WORD6_MAX

Maximum value representable by a Word6 (+364).

WORD6_MIN

Minimum value representable by a Word6 (-364).

Type Aliases

Result

Result type alias for ternary-rs operations.