base/syscall/
pio.rs

1/// A generic PIO interface.
2#[derive(Copy, Clone)]
3pub struct Pio<T> {
4   port: u16,
5   value: PhantomData<T>,
6}
7
8impl<T> Pio<T> {
9   /// Create a new PIO instance with the specified port.
10   ///
11   /// # Arguments
12   ///
13   /// * `port` - The port number.
14   ///
15   /// # Returns
16   ///
17   /// A new `Pio` instance.
18   pub const fn new(port: u16) -> Self {
19      return Pio{
20         port,
21         value: PhantomData
22      };
23   }
24}
25
26/// Read/write for `byte` PIO.
27impl HardwareIo for Pio<u8> {
28   type Value = u8;
29
30   fn read(&self) -> Self::Value {
31      let value: u8;
32
33      unsafe{
34         #[cfg(any(target_arch="x86", target_arch="x86_64"))]
35         asm!("in al, dx", in("dx") self.port, out("al") value, options(nostack, nomem, preserves_flags));
36
37         // TODO: implement ARM and RISC-V read operations.
38      }
39
40      return value;
41   }
42
43   fn write(&mut self, value: Self::Value) {
44      unsafe {
45         #[cfg(any(target_arch="x86", target_arch="x86_64"))]
46         asm!("out dx, al", in("dx") self.port, in("al") value, options(nostack, nomem, preserves_flags));
47
48         // TODO: implement ARM and RISC-V write operations.
49      }
50   }
51}
52
53/// Read/write for `word` PIO.
54impl HardwareIo for Pio<u16> {
55   type Value = u16;
56
57   fn read(&self) -> Self::Value {
58      let value: u16;
59
60      unsafe{
61         #[cfg(any(target_arch="x86", target_arch="x86_64"))]
62         asm!("in ax, dx", in("dx") self.port, out("ax") value, options(nostack, nomem, preserves_flags));
63
64         // TODO: implement ARM and RISC-V word read operations.
65      }
66
67      return value;
68   }
69
70   fn write(&mut self, value: Self::Value) {
71      unsafe{
72         #[cfg(any(target_arch="x86", target_arch="x86_64"))]
73         asm!("out dx, ax", in("dx") self.port, in("ax") value, options(nostack, nomem, preserves_flags));
74
75         // TODO: implement ARM and RISC-V word write operations.
76      }
77   }
78}
79
80/// Read/write for `dword` PIO.
81impl HardwareIo for Pio<u32> {
82   type Value = u32;
83
84   fn read(&self) -> Self::Value {
85      let value: u32;
86
87      unsafe{
88         #[cfg(target_arch="x86_64")]
89         asm!("in eax, dx", in("dx") self.port, out("eax") value, options(nostack, nomem, preserves_flags));
90
91         // TODO: implement ARM and RISC-V dword read operations.
92      }
93
94      return value;
95   }
96
97   fn write(&mut self, value: Self::Value) {
98      unsafe{
99         #[cfg(target_arch="x86_64")]
100         asm!("out dx, eax", in("dx") self.port, in("eax") value, options(nostack, nomem, preserves_flags));
101
102         // TODO: implement ARM and RISC-V dword write operations.
103      }
104   }
105}
106
107// IMPORTS //
108
109use {
110   crate::io::HardwareIo,
111   core::{
112      arch::asm,
113      marker::PhantomData,
114   },
115};
base/syscall/pio.rs

base/syscall/
pio.rs
