pub trait BusLine {
// Provided methods
fn read_u32(&mut self, addr: u32) -> Result<u32, String> { ... }
fn write_u32(&mut self, addr: u32, _data: u32) -> Result<(), String> { ... }
fn read_u16(&mut self, addr: u32) -> Result<u16, String> { ... }
fn write_u16(&mut self, addr: u32, _data: u16) -> Result<(), String> { ... }
fn read_u8(&mut self, addr: u32) -> Result<u8, String> { ... }
fn write_u8(&mut self, addr: u32, _data: u8) -> Result<(), String> { ... }
}
Expand description
A notion of a Busline, which is an interface to interact with memory mapped devices it can be a memory, or other stuff.
Here we implement the behavior for read/write
for each size of data (u32, u16, u8).