Crate topstitch

Structs

• Funnel
• ModDef
  Represents a module definition, like module <mod_def_name> ... endmodule in Verilog.
• ModDefCore
  Data structure representing a module definition.
• ModInst
  Represents an instance of a module definition, like <mod_def_name> <mod_inst_name> ( ... ); in Verilog.
• PipelineConfig
• PortSlice
  Represents a slice of a port, which may be on a module definition or on a module instance.

Enums

• IO
  Represents the direction (Input or Output) and bit width of a port.
• Intf
  Represents an interface on a module definition or module instance. Interfaces are used to connect modules together by function name.
• Port
  Represents a port on a module definition or a module instance.
• Usage
  Represents how a module definition should be used when validating and/or emitting Verilog.

Traits

• ConvertibleToPortSlice
  Indicates that a type can be converted to a PortSlice. Port and PortSlice both implement this trait, which makes it easier to perform the same operations on both.