tmc2209_uart/registers/
otp_read.rs

1//! OTP_READ - OTP memory read register (0x05)
2
3use super::{Address, ReadableRegister, Register};
4
5/// OTP memory read register.
6///
7/// Contains the power-up defaults stored in OTP memory.
8#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
9#[cfg_attr(feature = "defmt", derive(defmt::Format))]
10pub struct OtpRead(u32);
11
12impl OtpRead {
13    /// FCLKTRIM value (0-31).
14    ///
15    /// Factory-programmed clock frequency trim.
16    /// **Do not alter - differs between individual ICs.**
17    pub fn otp_fclktrim(&self) -> u8 {
18        (self.0 & 0x1F) as u8
19    }
20
21    /// OTTRIM value.
22    ///
23    /// - 0: OT=143°C
24    /// - 1: OT=150°C
25    pub fn otp_ottrim(&self) -> bool {
26        self.0 & (1 << 5) != 0
27    }
28
29    /// Internal Rsense default.
30    ///
31    /// - `true`: Internal sense resistors
32    /// - `false`: External sense resistors
33    pub fn otp_internal_rsense(&self) -> bool {
34        self.0 & (1 << 6) != 0
35    }
36
37    /// TBL default.
38    ///
39    /// - `false`: TBL=0b10
40    /// - `true`: TBL=0b01
41    pub fn otp_tbl(&self) -> bool {
42        self.0 & (1 << 7) != 0
43    }
44
45    /// PWM_GRAD default (0-15).
46    pub fn otp_pwm_grad(&self) -> u8 {
47        ((self.0 >> 8) & 0x0F) as u8
48    }
49
50    /// PWM_AUTOGRAD default.
51    pub fn otp_pwm_autograd(&self) -> bool {
52        self.0 & (1 << 12) != 0
53    }
54
55    /// TPWM_THRS default (0-7).
56    pub fn otp_tpwmthrs(&self) -> u8 {
57        ((self.0 >> 13) & 0x07) as u8
58    }
59
60    /// PWM_OFS default.
61    ///
62    /// - `false`: PWM_OFS=36
63    /// - `true`: PWM_OFS=0
64    pub fn otp_pwm_ofs(&self) -> bool {
65        self.0 & (1 << 16) != 0
66    }
67
68    /// PWM_REG default.
69    ///
70    /// - `false`: PWM_REG=0b1000
71    /// - `true`: PWM_REG=0b0010
72    pub fn otp_pwm_reg(&self) -> bool {
73        self.0 & (1 << 17) != 0
74    }
75
76    /// PWM_FREQ default.
77    ///
78    /// - `false`: PWM_FREQ=0b01
79    /// - `true`: PWM_FREQ=0b10
80    pub fn otp_pwm_freq(&self) -> bool {
81        self.0 & (1 << 18) != 0
82    }
83
84    /// IHOLDDELAY default (0-3).
85    pub fn otp_iholddelay(&self) -> u8 {
86        ((self.0 >> 19) & 0x03) as u8
87    }
88
89    /// IHOLD default (0-3).
90    pub fn otp_ihold(&self) -> u8 {
91        ((self.0 >> 21) & 0x03) as u8
92    }
93
94    /// SpreadCycle enabled by default.
95    ///
96    /// - `true`: SpreadCycle mode
97    /// - `false`: StealthChop mode
98    pub fn otp_en_spreadcycle(&self) -> bool {
99        self.0 & (1 << 23) != 0
100    }
101
102    /// Get the raw register value.
103    pub fn raw(&self) -> u32 {
104        self.0
105    }
106
107    /// Create from raw value.
108    pub fn from_raw(value: u32) -> Self {
109        Self(value)
110    }
111}
112
113impl Register for OtpRead {
114    const ADDRESS: Address = Address::OtpRead;
115}
116
117impl ReadableRegister for OtpRead {}
118
119impl From<u32> for OtpRead {
120    fn from(value: u32) -> Self {
121        Self(value)
122    }
123}
124
125impl From<OtpRead> for u32 {
126    fn from(reg: OtpRead) -> u32 {
127        reg.0
128    }
129}
tmc2209_uart/registers/otp_read.rs

tmc2209_uart/registers/
otp_read.rs
