1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - PWM Master Control"]
5 pub ctl: CTL,
6 #[doc = "0x04 - PWM Time Base Sync"]
7 pub sync: SYNC,
8 #[doc = "0x08 - PWM Output Enable"]
9 pub enable: ENABLE,
10 #[doc = "0x0c - PWM Output Inversion"]
11 pub invert: INVERT,
12 #[doc = "0x10 - PWM Output Fault"]
13 pub fault: FAULT,
14 #[doc = "0x14 - PWM Interrupt Enable"]
15 pub inten: INTEN,
16 #[doc = "0x18 - PWM Raw Interrupt Status"]
17 pub ris: RIS,
18 #[doc = "0x1c - PWM Interrupt Status and Clear"]
19 pub isc: ISC,
20 #[doc = "0x20 - PWM Status"]
21 pub status: STATUS,
22 #[doc = "0x24 - PWM Fault Condition Value"]
23 pub faultval: FAULTVAL,
24 #[doc = "0x28 - PWM Enable Update"]
25 pub enupd: ENUPD,
26 _reserved11: [u8; 20usize],
27 #[doc = "0x40 - PWM0 Control"]
28 pub _0_ctl: _0_CTL,
29 #[doc = "0x44 - PWM0 Interrupt and Trigger Enable"]
30 pub _0_inten: _0_INTEN,
31 #[doc = "0x48 - PWM0 Raw Interrupt Status"]
32 pub _0_ris: _0_RIS,
33 #[doc = "0x4c - PWM0 Interrupt Status and Clear"]
34 pub _0_isc: _0_ISC,
35 #[doc = "0x50 - PWM0 Load"]
36 pub _0_load: _0_LOAD,
37 #[doc = "0x54 - PWM0 Counter"]
38 pub _0_count: _0_COUNT,
39 #[doc = "0x58 - PWM0 Compare A"]
40 pub _0_cmpa: _0_CMPA,
41 #[doc = "0x5c - PWM0 Compare B"]
42 pub _0_cmpb: _0_CMPB,
43 #[doc = "0x60 - PWM0 Generator A Control"]
44 pub _0_gena: _0_GENA,
45 #[doc = "0x64 - PWM0 Generator B Control"]
46 pub _0_genb: _0_GENB,
47 #[doc = "0x68 - PWM0 Dead-Band Control"]
48 pub _0_dbctl: _0_DBCTL,
49 #[doc = "0x6c - PWM0 Dead-Band Rising-Edge Delay"]
50 pub _0_dbrise: _0_DBRISE,
51 #[doc = "0x70 - PWM0 Dead-Band Falling-Edge-Delay"]
52 pub _0_dbfall: _0_DBFALL,
53 #[doc = "0x74 - PWM0 Fault Source 0"]
54 pub _0_fltsrc0: _0_FLTSRC0,
55 #[doc = "0x78 - PWM0 Fault Source 1"]
56 pub _0_fltsrc1: _0_FLTSRC1,
57 #[doc = "0x7c - PWM0 Minimum Fault Period"]
58 pub _0_minfltper: _0_MINFLTPER,
59 #[doc = "0x80 - PWM1 Control"]
60 pub _1_ctl: _1_CTL,
61 #[doc = "0x84 - PWM1 Interrupt and Trigger Enable"]
62 pub _1_inten: _1_INTEN,
63 #[doc = "0x88 - PWM1 Raw Interrupt Status"]
64 pub _1_ris: _1_RIS,
65 #[doc = "0x8c - PWM1 Interrupt Status and Clear"]
66 pub _1_isc: _1_ISC,
67 #[doc = "0x90 - PWM1 Load"]
68 pub _1_load: _1_LOAD,
69 #[doc = "0x94 - PWM1 Counter"]
70 pub _1_count: _1_COUNT,
71 #[doc = "0x98 - PWM1 Compare A"]
72 pub _1_cmpa: _1_CMPA,
73 #[doc = "0x9c - PWM1 Compare B"]
74 pub _1_cmpb: _1_CMPB,
75 #[doc = "0xa0 - PWM1 Generator A Control"]
76 pub _1_gena: _1_GENA,
77 #[doc = "0xa4 - PWM1 Generator B Control"]
78 pub _1_genb: _1_GENB,
79 #[doc = "0xa8 - PWM1 Dead-Band Control"]
80 pub _1_dbctl: _1_DBCTL,
81 #[doc = "0xac - PWM1 Dead-Band Rising-Edge Delay"]
82 pub _1_dbrise: _1_DBRISE,
83 #[doc = "0xb0 - PWM1 Dead-Band Falling-Edge-Delay"]
84 pub _1_dbfall: _1_DBFALL,
85 #[doc = "0xb4 - PWM1 Fault Source 0"]
86 pub _1_fltsrc0: _1_FLTSRC0,
87 #[doc = "0xb8 - PWM1 Fault Source 1"]
88 pub _1_fltsrc1: _1_FLTSRC1,
89 #[doc = "0xbc - PWM1 Minimum Fault Period"]
90 pub _1_minfltper: _1_MINFLTPER,
91 #[doc = "0xc0 - PWM2 Control"]
92 pub _2_ctl: _2_CTL,
93 #[doc = "0xc4 - PWM2 Interrupt and Trigger Enable"]
94 pub _2_inten: _2_INTEN,
95 #[doc = "0xc8 - PWM2 Raw Interrupt Status"]
96 pub _2_ris: _2_RIS,
97 #[doc = "0xcc - PWM2 Interrupt Status and Clear"]
98 pub _2_isc: _2_ISC,
99 #[doc = "0xd0 - PWM2 Load"]
100 pub _2_load: _2_LOAD,
101 #[doc = "0xd4 - PWM2 Counter"]
102 pub _2_count: _2_COUNT,
103 #[doc = "0xd8 - PWM2 Compare A"]
104 pub _2_cmpa: _2_CMPA,
105 #[doc = "0xdc - PWM2 Compare B"]
106 pub _2_cmpb: _2_CMPB,
107 #[doc = "0xe0 - PWM2 Generator A Control"]
108 pub _2_gena: _2_GENA,
109 #[doc = "0xe4 - PWM2 Generator B Control"]
110 pub _2_genb: _2_GENB,
111 #[doc = "0xe8 - PWM2 Dead-Band Control"]
112 pub _2_dbctl: _2_DBCTL,
113 #[doc = "0xec - PWM2 Dead-Band Rising-Edge Delay"]
114 pub _2_dbrise: _2_DBRISE,
115 #[doc = "0xf0 - PWM2 Dead-Band Falling-Edge-Delay"]
116 pub _2_dbfall: _2_DBFALL,
117 #[doc = "0xf4 - PWM2 Fault Source 0"]
118 pub _2_fltsrc0: _2_FLTSRC0,
119 #[doc = "0xf8 - PWM2 Fault Source 1"]
120 pub _2_fltsrc1: _2_FLTSRC1,
121 #[doc = "0xfc - PWM2 Minimum Fault Period"]
122 pub _2_minfltper: _2_MINFLTPER,
123 #[doc = "0x100 - PWM3 Control"]
124 pub _3_ctl: _3_CTL,
125 #[doc = "0x104 - PWM3 Interrupt and Trigger Enable"]
126 pub _3_inten: _3_INTEN,
127 #[doc = "0x108 - PWM3 Raw Interrupt Status"]
128 pub _3_ris: _3_RIS,
129 #[doc = "0x10c - PWM3 Interrupt Status and Clear"]
130 pub _3_isc: _3_ISC,
131 #[doc = "0x110 - PWM3 Load"]
132 pub _3_load: _3_LOAD,
133 #[doc = "0x114 - PWM3 Counter"]
134 pub _3_count: _3_COUNT,
135 #[doc = "0x118 - PWM3 Compare A"]
136 pub _3_cmpa: _3_CMPA,
137 #[doc = "0x11c - PWM3 Compare B"]
138 pub _3_cmpb: _3_CMPB,
139 #[doc = "0x120 - PWM3 Generator A Control"]
140 pub _3_gena: _3_GENA,
141 #[doc = "0x124 - PWM3 Generator B Control"]
142 pub _3_genb: _3_GENB,
143 #[doc = "0x128 - PWM3 Dead-Band Control"]
144 pub _3_dbctl: _3_DBCTL,
145 #[doc = "0x12c - PWM3 Dead-Band Rising-Edge Delay"]
146 pub _3_dbrise: _3_DBRISE,
147 #[doc = "0x130 - PWM3 Dead-Band Falling-Edge-Delay"]
148 pub _3_dbfall: _3_DBFALL,
149 #[doc = "0x134 - PWM3 Fault Source 0"]
150 pub _3_fltsrc0: _3_FLTSRC0,
151 #[doc = "0x138 - PWM3 Fault Source 1"]
152 pub _3_fltsrc1: _3_FLTSRC1,
153 #[doc = "0x13c - PWM3 Minimum Fault Period"]
154 pub _3_minfltper: _3_MINFLTPER,
155 _reserved75: [u8; 1728usize],
156 #[doc = "0x800 - PWM0 Fault Pin Logic Sense"]
157 pub _0_fltsen: _0_FLTSEN,
158 #[doc = "0x804 - PWM0 Fault Status 0"]
159 pub _0_fltstat0: _0_FLTSTAT0,
160 #[doc = "0x808 - PWM0 Fault Status 1"]
161 pub _0_fltstat1: _0_FLTSTAT1,
162 _reserved78: [u8; 116usize],
163 #[doc = "0x880 - PWM1 Fault Pin Logic Sense"]
164 pub _1_fltsen: _1_FLTSEN,
165 #[doc = "0x884 - PWM1 Fault Status 0"]
166 pub _1_fltstat0: _1_FLTSTAT0,
167 #[doc = "0x888 - PWM1 Fault Status 1"]
168 pub _1_fltstat1: _1_FLTSTAT1,
169 _reserved81: [u8; 116usize],
170 #[doc = "0x900 - PWM2 Fault Pin Logic Sense"]
171 pub _2_fltsen: _2_FLTSEN,
172 #[doc = "0x904 - PWM2 Fault Status 0"]
173 pub _2_fltstat0: _2_FLTSTAT0,
174 #[doc = "0x908 - PWM2 Fault Status 1"]
175 pub _2_fltstat1: _2_FLTSTAT1,
176 _reserved84: [u8; 116usize],
177 #[doc = "0x980 - PWM3 Fault Pin Logic Sense"]
178 pub _3_fltsen: _3_FLTSEN,
179 #[doc = "0x984 - PWM3 Fault Status 0"]
180 pub _3_fltstat0: _3_FLTSTAT0,
181 #[doc = "0x988 - PWM3 Fault Status 1"]
182 pub _3_fltstat1: _3_FLTSTAT1,
183 _reserved87: [u8; 1588usize],
184 #[doc = "0xfc0 - PWM Peripheral Properties"]
185 pub pp: PP,
186 _reserved88: [u8; 4usize],
187 #[doc = "0xfc8 - PWM Clock Configuration"]
188 pub cc: CC,
189}
190#[doc = "PWM Master Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](ctl) module"]
191pub type CTL = crate::Reg<u32, _CTL>;
192#[allow(missing_docs)]
193#[doc(hidden)]
194pub struct _CTL;
195#[doc = "`read()` method returns [ctl::R](ctl::R) reader structure"]
196impl crate::Readable for CTL {}
197#[doc = "`write(|w| ..)` method takes [ctl::W](ctl::W) writer structure"]
198impl crate::Writable for CTL {}
199#[doc = "PWM Master Control"]
200pub mod ctl;
201#[doc = "PWM Time Base Sync\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sync](sync) module"]
202pub type SYNC = crate::Reg<u32, _SYNC>;
203#[allow(missing_docs)]
204#[doc(hidden)]
205pub struct _SYNC;
206#[doc = "`read()` method returns [sync::R](sync::R) reader structure"]
207impl crate::Readable for SYNC {}
208#[doc = "`write(|w| ..)` method takes [sync::W](sync::W) writer structure"]
209impl crate::Writable for SYNC {}
210#[doc = "PWM Time Base Sync"]
211pub mod sync;
212#[doc = "PWM Output Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](enable) module"]
213pub type ENABLE = crate::Reg<u32, _ENABLE>;
214#[allow(missing_docs)]
215#[doc(hidden)]
216pub struct _ENABLE;
217#[doc = "`read()` method returns [enable::R](enable::R) reader structure"]
218impl crate::Readable for ENABLE {}
219#[doc = "`write(|w| ..)` method takes [enable::W](enable::W) writer structure"]
220impl crate::Writable for ENABLE {}
221#[doc = "PWM Output Enable"]
222pub mod enable;
223#[doc = "PWM Output Inversion\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [invert](invert) module"]
224pub type INVERT = crate::Reg<u32, _INVERT>;
225#[allow(missing_docs)]
226#[doc(hidden)]
227pub struct _INVERT;
228#[doc = "`read()` method returns [invert::R](invert::R) reader structure"]
229impl crate::Readable for INVERT {}
230#[doc = "`write(|w| ..)` method takes [invert::W](invert::W) writer structure"]
231impl crate::Writable for INVERT {}
232#[doc = "PWM Output Inversion"]
233pub mod invert;
234#[doc = "PWM Output Fault\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fault](fault) module"]
235pub type FAULT = crate::Reg<u32, _FAULT>;
236#[allow(missing_docs)]
237#[doc(hidden)]
238pub struct _FAULT;
239#[doc = "`read()` method returns [fault::R](fault::R) reader structure"]
240impl crate::Readable for FAULT {}
241#[doc = "`write(|w| ..)` method takes [fault::W](fault::W) writer structure"]
242impl crate::Writable for FAULT {}
243#[doc = "PWM Output Fault"]
244pub mod fault;
245#[doc = "PWM Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](inten) module"]
246pub type INTEN = crate::Reg<u32, _INTEN>;
247#[allow(missing_docs)]
248#[doc(hidden)]
249pub struct _INTEN;
250#[doc = "`read()` method returns [inten::R](inten::R) reader structure"]
251impl crate::Readable for INTEN {}
252#[doc = "`write(|w| ..)` method takes [inten::W](inten::W) writer structure"]
253impl crate::Writable for INTEN {}
254#[doc = "PWM Interrupt Enable"]
255pub mod inten;
256#[doc = "PWM Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](ris) module"]
257pub type RIS = crate::Reg<u32, _RIS>;
258#[allow(missing_docs)]
259#[doc(hidden)]
260pub struct _RIS;
261#[doc = "`read()` method returns [ris::R](ris::R) reader structure"]
262impl crate::Readable for RIS {}
263#[doc = "PWM Raw Interrupt Status"]
264pub mod ris;
265#[doc = "PWM Interrupt Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isc](isc) module"]
266pub type ISC = crate::Reg<u32, _ISC>;
267#[allow(missing_docs)]
268#[doc(hidden)]
269pub struct _ISC;
270#[doc = "`read()` method returns [isc::R](isc::R) reader structure"]
271impl crate::Readable for ISC {}
272#[doc = "`write(|w| ..)` method takes [isc::W](isc::W) writer structure"]
273impl crate::Writable for ISC {}
274#[doc = "PWM Interrupt Status and Clear"]
275pub mod isc;
276#[doc = "PWM Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"]
277pub type STATUS = crate::Reg<u32, _STATUS>;
278#[allow(missing_docs)]
279#[doc(hidden)]
280pub struct _STATUS;
281#[doc = "`read()` method returns [status::R](status::R) reader structure"]
282impl crate::Readable for STATUS {}
283#[doc = "PWM Status"]
284pub mod status;
285#[doc = "PWM Fault Condition Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [faultval](faultval) module"]
286pub type FAULTVAL = crate::Reg<u32, _FAULTVAL>;
287#[allow(missing_docs)]
288#[doc(hidden)]
289pub struct _FAULTVAL;
290#[doc = "`read()` method returns [faultval::R](faultval::R) reader structure"]
291impl crate::Readable for FAULTVAL {}
292#[doc = "`write(|w| ..)` method takes [faultval::W](faultval::W) writer structure"]
293impl crate::Writable for FAULTVAL {}
294#[doc = "PWM Fault Condition Value"]
295pub mod faultval;
296#[doc = "PWM Enable Update\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enupd](enupd) module"]
297pub type ENUPD = crate::Reg<u32, _ENUPD>;
298#[allow(missing_docs)]
299#[doc(hidden)]
300pub struct _ENUPD;
301#[doc = "`read()` method returns [enupd::R](enupd::R) reader structure"]
302impl crate::Readable for ENUPD {}
303#[doc = "`write(|w| ..)` method takes [enupd::W](enupd::W) writer structure"]
304impl crate::Writable for ENUPD {}
305#[doc = "PWM Enable Update"]
306pub mod enupd;
307#[doc = "PWM0 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_ctl](_0_ctl) module"]
308pub type _0_CTL = crate::Reg<u32, __0_CTL>;
309#[allow(missing_docs)]
310#[doc(hidden)]
311pub struct __0_CTL;
312#[doc = "`read()` method returns [_0_ctl::R](_0_ctl::R) reader structure"]
313impl crate::Readable for _0_CTL {}
314#[doc = "`write(|w| ..)` method takes [_0_ctl::W](_0_ctl::W) writer structure"]
315impl crate::Writable for _0_CTL {}
316#[doc = "PWM0 Control"]
317pub mod _0_ctl;
318#[doc = "PWM0 Interrupt and Trigger Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_inten](_0_inten) module"]
319pub type _0_INTEN = crate::Reg<u32, __0_INTEN>;
320#[allow(missing_docs)]
321#[doc(hidden)]
322pub struct __0_INTEN;
323#[doc = "`read()` method returns [_0_inten::R](_0_inten::R) reader structure"]
324impl crate::Readable for _0_INTEN {}
325#[doc = "`write(|w| ..)` method takes [_0_inten::W](_0_inten::W) writer structure"]
326impl crate::Writable for _0_INTEN {}
327#[doc = "PWM0 Interrupt and Trigger Enable"]
328pub mod _0_inten;
329#[doc = "PWM0 Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_ris](_0_ris) module"]
330pub type _0_RIS = crate::Reg<u32, __0_RIS>;
331#[allow(missing_docs)]
332#[doc(hidden)]
333pub struct __0_RIS;
334#[doc = "`read()` method returns [_0_ris::R](_0_ris::R) reader structure"]
335impl crate::Readable for _0_RIS {}
336#[doc = "PWM0 Raw Interrupt Status"]
337pub mod _0_ris;
338#[doc = "PWM0 Interrupt Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_isc](_0_isc) module"]
339pub type _0_ISC = crate::Reg<u32, __0_ISC>;
340#[allow(missing_docs)]
341#[doc(hidden)]
342pub struct __0_ISC;
343#[doc = "`read()` method returns [_0_isc::R](_0_isc::R) reader structure"]
344impl crate::Readable for _0_ISC {}
345#[doc = "`write(|w| ..)` method takes [_0_isc::W](_0_isc::W) writer structure"]
346impl crate::Writable for _0_ISC {}
347#[doc = "PWM0 Interrupt Status and Clear"]
348pub mod _0_isc;
349#[doc = "PWM0 Load\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_load](_0_load) module"]
350pub type _0_LOAD = crate::Reg<u32, __0_LOAD>;
351#[allow(missing_docs)]
352#[doc(hidden)]
353pub struct __0_LOAD;
354#[doc = "`read()` method returns [_0_load::R](_0_load::R) reader structure"]
355impl crate::Readable for _0_LOAD {}
356#[doc = "`write(|w| ..)` method takes [_0_load::W](_0_load::W) writer structure"]
357impl crate::Writable for _0_LOAD {}
358#[doc = "PWM0 Load"]
359pub mod _0_load;
360#[doc = "PWM0 Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_count](_0_count) module"]
361pub type _0_COUNT = crate::Reg<u32, __0_COUNT>;
362#[allow(missing_docs)]
363#[doc(hidden)]
364pub struct __0_COUNT;
365#[doc = "`read()` method returns [_0_count::R](_0_count::R) reader structure"]
366impl crate::Readable for _0_COUNT {}
367#[doc = "PWM0 Counter"]
368pub mod _0_count;
369#[doc = "PWM0 Compare A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_cmpa](_0_cmpa) module"]
370pub type _0_CMPA = crate::Reg<u32, __0_CMPA>;
371#[allow(missing_docs)]
372#[doc(hidden)]
373pub struct __0_CMPA;
374#[doc = "`read()` method returns [_0_cmpa::R](_0_cmpa::R) reader structure"]
375impl crate::Readable for _0_CMPA {}
376#[doc = "`write(|w| ..)` method takes [_0_cmpa::W](_0_cmpa::W) writer structure"]
377impl crate::Writable for _0_CMPA {}
378#[doc = "PWM0 Compare A"]
379pub mod _0_cmpa;
380#[doc = "PWM0 Compare B\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_cmpb](_0_cmpb) module"]
381pub type _0_CMPB = crate::Reg<u32, __0_CMPB>;
382#[allow(missing_docs)]
383#[doc(hidden)]
384pub struct __0_CMPB;
385#[doc = "`read()` method returns [_0_cmpb::R](_0_cmpb::R) reader structure"]
386impl crate::Readable for _0_CMPB {}
387#[doc = "`write(|w| ..)` method takes [_0_cmpb::W](_0_cmpb::W) writer structure"]
388impl crate::Writable for _0_CMPB {}
389#[doc = "PWM0 Compare B"]
390pub mod _0_cmpb;
391#[doc = "PWM0 Generator A Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_gena](_0_gena) module"]
392pub type _0_GENA = crate::Reg<u32, __0_GENA>;
393#[allow(missing_docs)]
394#[doc(hidden)]
395pub struct __0_GENA;
396#[doc = "`read()` method returns [_0_gena::R](_0_gena::R) reader structure"]
397impl crate::Readable for _0_GENA {}
398#[doc = "`write(|w| ..)` method takes [_0_gena::W](_0_gena::W) writer structure"]
399impl crate::Writable for _0_GENA {}
400#[doc = "PWM0 Generator A Control"]
401pub mod _0_gena;
402#[doc = "PWM0 Generator B Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_genb](_0_genb) module"]
403pub type _0_GENB = crate::Reg<u32, __0_GENB>;
404#[allow(missing_docs)]
405#[doc(hidden)]
406pub struct __0_GENB;
407#[doc = "`read()` method returns [_0_genb::R](_0_genb::R) reader structure"]
408impl crate::Readable for _0_GENB {}
409#[doc = "`write(|w| ..)` method takes [_0_genb::W](_0_genb::W) writer structure"]
410impl crate::Writable for _0_GENB {}
411#[doc = "PWM0 Generator B Control"]
412pub mod _0_genb;
413#[doc = "PWM0 Dead-Band Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_dbctl](_0_dbctl) module"]
414pub type _0_DBCTL = crate::Reg<u32, __0_DBCTL>;
415#[allow(missing_docs)]
416#[doc(hidden)]
417pub struct __0_DBCTL;
418#[doc = "`read()` method returns [_0_dbctl::R](_0_dbctl::R) reader structure"]
419impl crate::Readable for _0_DBCTL {}
420#[doc = "`write(|w| ..)` method takes [_0_dbctl::W](_0_dbctl::W) writer structure"]
421impl crate::Writable for _0_DBCTL {}
422#[doc = "PWM0 Dead-Band Control"]
423pub mod _0_dbctl;
424#[doc = "PWM0 Dead-Band Rising-Edge Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_dbrise](_0_dbrise) module"]
425pub type _0_DBRISE = crate::Reg<u32, __0_DBRISE>;
426#[allow(missing_docs)]
427#[doc(hidden)]
428pub struct __0_DBRISE;
429#[doc = "`read()` method returns [_0_dbrise::R](_0_dbrise::R) reader structure"]
430impl crate::Readable for _0_DBRISE {}
431#[doc = "`write(|w| ..)` method takes [_0_dbrise::W](_0_dbrise::W) writer structure"]
432impl crate::Writable for _0_DBRISE {}
433#[doc = "PWM0 Dead-Band Rising-Edge Delay"]
434pub mod _0_dbrise;
435#[doc = "PWM0 Dead-Band Falling-Edge-Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_dbfall](_0_dbfall) module"]
436pub type _0_DBFALL = crate::Reg<u32, __0_DBFALL>;
437#[allow(missing_docs)]
438#[doc(hidden)]
439pub struct __0_DBFALL;
440#[doc = "`read()` method returns [_0_dbfall::R](_0_dbfall::R) reader structure"]
441impl crate::Readable for _0_DBFALL {}
442#[doc = "`write(|w| ..)` method takes [_0_dbfall::W](_0_dbfall::W) writer structure"]
443impl crate::Writable for _0_DBFALL {}
444#[doc = "PWM0 Dead-Band Falling-Edge-Delay"]
445pub mod _0_dbfall;
446#[doc = "PWM0 Fault Source 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_fltsrc0](_0_fltsrc0) module"]
447pub type _0_FLTSRC0 = crate::Reg<u32, __0_FLTSRC0>;
448#[allow(missing_docs)]
449#[doc(hidden)]
450pub struct __0_FLTSRC0;
451#[doc = "`read()` method returns [_0_fltsrc0::R](_0_fltsrc0::R) reader structure"]
452impl crate::Readable for _0_FLTSRC0 {}
453#[doc = "`write(|w| ..)` method takes [_0_fltsrc0::W](_0_fltsrc0::W) writer structure"]
454impl crate::Writable for _0_FLTSRC0 {}
455#[doc = "PWM0 Fault Source 0"]
456pub mod _0_fltsrc0;
457#[doc = "PWM0 Fault Source 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_fltsrc1](_0_fltsrc1) module"]
458pub type _0_FLTSRC1 = crate::Reg<u32, __0_FLTSRC1>;
459#[allow(missing_docs)]
460#[doc(hidden)]
461pub struct __0_FLTSRC1;
462#[doc = "`read()` method returns [_0_fltsrc1::R](_0_fltsrc1::R) reader structure"]
463impl crate::Readable for _0_FLTSRC1 {}
464#[doc = "`write(|w| ..)` method takes [_0_fltsrc1::W](_0_fltsrc1::W) writer structure"]
465impl crate::Writable for _0_FLTSRC1 {}
466#[doc = "PWM0 Fault Source 1"]
467pub mod _0_fltsrc1;
468#[doc = "PWM0 Minimum Fault Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_minfltper](_0_minfltper) module"]
469pub type _0_MINFLTPER = crate::Reg<u32, __0_MINFLTPER>;
470#[allow(missing_docs)]
471#[doc(hidden)]
472pub struct __0_MINFLTPER;
473#[doc = "`read()` method returns [_0_minfltper::R](_0_minfltper::R) reader structure"]
474impl crate::Readable for _0_MINFLTPER {}
475#[doc = "`write(|w| ..)` method takes [_0_minfltper::W](_0_minfltper::W) writer structure"]
476impl crate::Writable for _0_MINFLTPER {}
477#[doc = "PWM0 Minimum Fault Period"]
478pub mod _0_minfltper;
479#[doc = "PWM1 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_ctl](_1_ctl) module"]
480pub type _1_CTL = crate::Reg<u32, __1_CTL>;
481#[allow(missing_docs)]
482#[doc(hidden)]
483pub struct __1_CTL;
484#[doc = "`read()` method returns [_1_ctl::R](_1_ctl::R) reader structure"]
485impl crate::Readable for _1_CTL {}
486#[doc = "`write(|w| ..)` method takes [_1_ctl::W](_1_ctl::W) writer structure"]
487impl crate::Writable for _1_CTL {}
488#[doc = "PWM1 Control"]
489pub mod _1_ctl;
490#[doc = "PWM1 Interrupt and Trigger Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_inten](_1_inten) module"]
491pub type _1_INTEN = crate::Reg<u32, __1_INTEN>;
492#[allow(missing_docs)]
493#[doc(hidden)]
494pub struct __1_INTEN;
495#[doc = "`read()` method returns [_1_inten::R](_1_inten::R) reader structure"]
496impl crate::Readable for _1_INTEN {}
497#[doc = "`write(|w| ..)` method takes [_1_inten::W](_1_inten::W) writer structure"]
498impl crate::Writable for _1_INTEN {}
499#[doc = "PWM1 Interrupt and Trigger Enable"]
500pub mod _1_inten;
501#[doc = "PWM1 Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_ris](_1_ris) module"]
502pub type _1_RIS = crate::Reg<u32, __1_RIS>;
503#[allow(missing_docs)]
504#[doc(hidden)]
505pub struct __1_RIS;
506#[doc = "`read()` method returns [_1_ris::R](_1_ris::R) reader structure"]
507impl crate::Readable for _1_RIS {}
508#[doc = "PWM1 Raw Interrupt Status"]
509pub mod _1_ris;
510#[doc = "PWM1 Interrupt Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_isc](_1_isc) module"]
511pub type _1_ISC = crate::Reg<u32, __1_ISC>;
512#[allow(missing_docs)]
513#[doc(hidden)]
514pub struct __1_ISC;
515#[doc = "`read()` method returns [_1_isc::R](_1_isc::R) reader structure"]
516impl crate::Readable for _1_ISC {}
517#[doc = "`write(|w| ..)` method takes [_1_isc::W](_1_isc::W) writer structure"]
518impl crate::Writable for _1_ISC {}
519#[doc = "PWM1 Interrupt Status and Clear"]
520pub mod _1_isc;
521#[doc = "PWM1 Load\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_load](_1_load) module"]
522pub type _1_LOAD = crate::Reg<u32, __1_LOAD>;
523#[allow(missing_docs)]
524#[doc(hidden)]
525pub struct __1_LOAD;
526#[doc = "`read()` method returns [_1_load::R](_1_load::R) reader structure"]
527impl crate::Readable for _1_LOAD {}
528#[doc = "`write(|w| ..)` method takes [_1_load::W](_1_load::W) writer structure"]
529impl crate::Writable for _1_LOAD {}
530#[doc = "PWM1 Load"]
531pub mod _1_load;
532#[doc = "PWM1 Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_count](_1_count) module"]
533pub type _1_COUNT = crate::Reg<u32, __1_COUNT>;
534#[allow(missing_docs)]
535#[doc(hidden)]
536pub struct __1_COUNT;
537#[doc = "`read()` method returns [_1_count::R](_1_count::R) reader structure"]
538impl crate::Readable for _1_COUNT {}
539#[doc = "PWM1 Counter"]
540pub mod _1_count;
541#[doc = "PWM1 Compare A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_cmpa](_1_cmpa) module"]
542pub type _1_CMPA = crate::Reg<u32, __1_CMPA>;
543#[allow(missing_docs)]
544#[doc(hidden)]
545pub struct __1_CMPA;
546#[doc = "`read()` method returns [_1_cmpa::R](_1_cmpa::R) reader structure"]
547impl crate::Readable for _1_CMPA {}
548#[doc = "`write(|w| ..)` method takes [_1_cmpa::W](_1_cmpa::W) writer structure"]
549impl crate::Writable for _1_CMPA {}
550#[doc = "PWM1 Compare A"]
551pub mod _1_cmpa;
552#[doc = "PWM1 Compare B\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_cmpb](_1_cmpb) module"]
553pub type _1_CMPB = crate::Reg<u32, __1_CMPB>;
554#[allow(missing_docs)]
555#[doc(hidden)]
556pub struct __1_CMPB;
557#[doc = "`read()` method returns [_1_cmpb::R](_1_cmpb::R) reader structure"]
558impl crate::Readable for _1_CMPB {}
559#[doc = "`write(|w| ..)` method takes [_1_cmpb::W](_1_cmpb::W) writer structure"]
560impl crate::Writable for _1_CMPB {}
561#[doc = "PWM1 Compare B"]
562pub mod _1_cmpb;
563#[doc = "PWM1 Generator A Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_gena](_1_gena) module"]
564pub type _1_GENA = crate::Reg<u32, __1_GENA>;
565#[allow(missing_docs)]
566#[doc(hidden)]
567pub struct __1_GENA;
568#[doc = "`read()` method returns [_1_gena::R](_1_gena::R) reader structure"]
569impl crate::Readable for _1_GENA {}
570#[doc = "`write(|w| ..)` method takes [_1_gena::W](_1_gena::W) writer structure"]
571impl crate::Writable for _1_GENA {}
572#[doc = "PWM1 Generator A Control"]
573pub mod _1_gena;
574#[doc = "PWM1 Generator B Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_genb](_1_genb) module"]
575pub type _1_GENB = crate::Reg<u32, __1_GENB>;
576#[allow(missing_docs)]
577#[doc(hidden)]
578pub struct __1_GENB;
579#[doc = "`read()` method returns [_1_genb::R](_1_genb::R) reader structure"]
580impl crate::Readable for _1_GENB {}
581#[doc = "`write(|w| ..)` method takes [_1_genb::W](_1_genb::W) writer structure"]
582impl crate::Writable for _1_GENB {}
583#[doc = "PWM1 Generator B Control"]
584pub mod _1_genb;
585#[doc = "PWM1 Dead-Band Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_dbctl](_1_dbctl) module"]
586pub type _1_DBCTL = crate::Reg<u32, __1_DBCTL>;
587#[allow(missing_docs)]
588#[doc(hidden)]
589pub struct __1_DBCTL;
590#[doc = "`read()` method returns [_1_dbctl::R](_1_dbctl::R) reader structure"]
591impl crate::Readable for _1_DBCTL {}
592#[doc = "`write(|w| ..)` method takes [_1_dbctl::W](_1_dbctl::W) writer structure"]
593impl crate::Writable for _1_DBCTL {}
594#[doc = "PWM1 Dead-Band Control"]
595pub mod _1_dbctl;
596#[doc = "PWM1 Dead-Band Rising-Edge Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_dbrise](_1_dbrise) module"]
597pub type _1_DBRISE = crate::Reg<u32, __1_DBRISE>;
598#[allow(missing_docs)]
599#[doc(hidden)]
600pub struct __1_DBRISE;
601#[doc = "`read()` method returns [_1_dbrise::R](_1_dbrise::R) reader structure"]
602impl crate::Readable for _1_DBRISE {}
603#[doc = "`write(|w| ..)` method takes [_1_dbrise::W](_1_dbrise::W) writer structure"]
604impl crate::Writable for _1_DBRISE {}
605#[doc = "PWM1 Dead-Band Rising-Edge Delay"]
606pub mod _1_dbrise;
607#[doc = "PWM1 Dead-Band Falling-Edge-Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_dbfall](_1_dbfall) module"]
608pub type _1_DBFALL = crate::Reg<u32, __1_DBFALL>;
609#[allow(missing_docs)]
610#[doc(hidden)]
611pub struct __1_DBFALL;
612#[doc = "`read()` method returns [_1_dbfall::R](_1_dbfall::R) reader structure"]
613impl crate::Readable for _1_DBFALL {}
614#[doc = "`write(|w| ..)` method takes [_1_dbfall::W](_1_dbfall::W) writer structure"]
615impl crate::Writable for _1_DBFALL {}
616#[doc = "PWM1 Dead-Band Falling-Edge-Delay"]
617pub mod _1_dbfall;
618#[doc = "PWM1 Fault Source 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_fltsrc0](_1_fltsrc0) module"]
619pub type _1_FLTSRC0 = crate::Reg<u32, __1_FLTSRC0>;
620#[allow(missing_docs)]
621#[doc(hidden)]
622pub struct __1_FLTSRC0;
623#[doc = "`read()` method returns [_1_fltsrc0::R](_1_fltsrc0::R) reader structure"]
624impl crate::Readable for _1_FLTSRC0 {}
625#[doc = "`write(|w| ..)` method takes [_1_fltsrc0::W](_1_fltsrc0::W) writer structure"]
626impl crate::Writable for _1_FLTSRC0 {}
627#[doc = "PWM1 Fault Source 0"]
628pub mod _1_fltsrc0;
629#[doc = "PWM1 Fault Source 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_fltsrc1](_1_fltsrc1) module"]
630pub type _1_FLTSRC1 = crate::Reg<u32, __1_FLTSRC1>;
631#[allow(missing_docs)]
632#[doc(hidden)]
633pub struct __1_FLTSRC1;
634#[doc = "`read()` method returns [_1_fltsrc1::R](_1_fltsrc1::R) reader structure"]
635impl crate::Readable for _1_FLTSRC1 {}
636#[doc = "`write(|w| ..)` method takes [_1_fltsrc1::W](_1_fltsrc1::W) writer structure"]
637impl crate::Writable for _1_FLTSRC1 {}
638#[doc = "PWM1 Fault Source 1"]
639pub mod _1_fltsrc1;
640#[doc = "PWM1 Minimum Fault Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_minfltper](_1_minfltper) module"]
641pub type _1_MINFLTPER = crate::Reg<u32, __1_MINFLTPER>;
642#[allow(missing_docs)]
643#[doc(hidden)]
644pub struct __1_MINFLTPER;
645#[doc = "`read()` method returns [_1_minfltper::R](_1_minfltper::R) reader structure"]
646impl crate::Readable for _1_MINFLTPER {}
647#[doc = "`write(|w| ..)` method takes [_1_minfltper::W](_1_minfltper::W) writer structure"]
648impl crate::Writable for _1_MINFLTPER {}
649#[doc = "PWM1 Minimum Fault Period"]
650pub mod _1_minfltper;
651#[doc = "PWM2 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_ctl](_2_ctl) module"]
652pub type _2_CTL = crate::Reg<u32, __2_CTL>;
653#[allow(missing_docs)]
654#[doc(hidden)]
655pub struct __2_CTL;
656#[doc = "`read()` method returns [_2_ctl::R](_2_ctl::R) reader structure"]
657impl crate::Readable for _2_CTL {}
658#[doc = "`write(|w| ..)` method takes [_2_ctl::W](_2_ctl::W) writer structure"]
659impl crate::Writable for _2_CTL {}
660#[doc = "PWM2 Control"]
661pub mod _2_ctl;
662#[doc = "PWM2 Interrupt and Trigger Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_inten](_2_inten) module"]
663pub type _2_INTEN = crate::Reg<u32, __2_INTEN>;
664#[allow(missing_docs)]
665#[doc(hidden)]
666pub struct __2_INTEN;
667#[doc = "`read()` method returns [_2_inten::R](_2_inten::R) reader structure"]
668impl crate::Readable for _2_INTEN {}
669#[doc = "`write(|w| ..)` method takes [_2_inten::W](_2_inten::W) writer structure"]
670impl crate::Writable for _2_INTEN {}
671#[doc = "PWM2 Interrupt and Trigger Enable"]
672pub mod _2_inten;
673#[doc = "PWM2 Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_ris](_2_ris) module"]
674pub type _2_RIS = crate::Reg<u32, __2_RIS>;
675#[allow(missing_docs)]
676#[doc(hidden)]
677pub struct __2_RIS;
678#[doc = "`read()` method returns [_2_ris::R](_2_ris::R) reader structure"]
679impl crate::Readable for _2_RIS {}
680#[doc = "PWM2 Raw Interrupt Status"]
681pub mod _2_ris;
682#[doc = "PWM2 Interrupt Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_isc](_2_isc) module"]
683pub type _2_ISC = crate::Reg<u32, __2_ISC>;
684#[allow(missing_docs)]
685#[doc(hidden)]
686pub struct __2_ISC;
687#[doc = "`read()` method returns [_2_isc::R](_2_isc::R) reader structure"]
688impl crate::Readable for _2_ISC {}
689#[doc = "`write(|w| ..)` method takes [_2_isc::W](_2_isc::W) writer structure"]
690impl crate::Writable for _2_ISC {}
691#[doc = "PWM2 Interrupt Status and Clear"]
692pub mod _2_isc;
693#[doc = "PWM2 Load\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_load](_2_load) module"]
694pub type _2_LOAD = crate::Reg<u32, __2_LOAD>;
695#[allow(missing_docs)]
696#[doc(hidden)]
697pub struct __2_LOAD;
698#[doc = "`read()` method returns [_2_load::R](_2_load::R) reader structure"]
699impl crate::Readable for _2_LOAD {}
700#[doc = "`write(|w| ..)` method takes [_2_load::W](_2_load::W) writer structure"]
701impl crate::Writable for _2_LOAD {}
702#[doc = "PWM2 Load"]
703pub mod _2_load;
704#[doc = "PWM2 Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_count](_2_count) module"]
705pub type _2_COUNT = crate::Reg<u32, __2_COUNT>;
706#[allow(missing_docs)]
707#[doc(hidden)]
708pub struct __2_COUNT;
709#[doc = "`read()` method returns [_2_count::R](_2_count::R) reader structure"]
710impl crate::Readable for _2_COUNT {}
711#[doc = "PWM2 Counter"]
712pub mod _2_count;
713#[doc = "PWM2 Compare A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_cmpa](_2_cmpa) module"]
714pub type _2_CMPA = crate::Reg<u32, __2_CMPA>;
715#[allow(missing_docs)]
716#[doc(hidden)]
717pub struct __2_CMPA;
718#[doc = "`read()` method returns [_2_cmpa::R](_2_cmpa::R) reader structure"]
719impl crate::Readable for _2_CMPA {}
720#[doc = "`write(|w| ..)` method takes [_2_cmpa::W](_2_cmpa::W) writer structure"]
721impl crate::Writable for _2_CMPA {}
722#[doc = "PWM2 Compare A"]
723pub mod _2_cmpa;
724#[doc = "PWM2 Compare B\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_cmpb](_2_cmpb) module"]
725pub type _2_CMPB = crate::Reg<u32, __2_CMPB>;
726#[allow(missing_docs)]
727#[doc(hidden)]
728pub struct __2_CMPB;
729#[doc = "`read()` method returns [_2_cmpb::R](_2_cmpb::R) reader structure"]
730impl crate::Readable for _2_CMPB {}
731#[doc = "`write(|w| ..)` method takes [_2_cmpb::W](_2_cmpb::W) writer structure"]
732impl crate::Writable for _2_CMPB {}
733#[doc = "PWM2 Compare B"]
734pub mod _2_cmpb;
735#[doc = "PWM2 Generator A Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_gena](_2_gena) module"]
736pub type _2_GENA = crate::Reg<u32, __2_GENA>;
737#[allow(missing_docs)]
738#[doc(hidden)]
739pub struct __2_GENA;
740#[doc = "`read()` method returns [_2_gena::R](_2_gena::R) reader structure"]
741impl crate::Readable for _2_GENA {}
742#[doc = "`write(|w| ..)` method takes [_2_gena::W](_2_gena::W) writer structure"]
743impl crate::Writable for _2_GENA {}
744#[doc = "PWM2 Generator A Control"]
745pub mod _2_gena;
746#[doc = "PWM2 Generator B Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_genb](_2_genb) module"]
747pub type _2_GENB = crate::Reg<u32, __2_GENB>;
748#[allow(missing_docs)]
749#[doc(hidden)]
750pub struct __2_GENB;
751#[doc = "`read()` method returns [_2_genb::R](_2_genb::R) reader structure"]
752impl crate::Readable for _2_GENB {}
753#[doc = "`write(|w| ..)` method takes [_2_genb::W](_2_genb::W) writer structure"]
754impl crate::Writable for _2_GENB {}
755#[doc = "PWM2 Generator B Control"]
756pub mod _2_genb;
757#[doc = "PWM2 Dead-Band Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_dbctl](_2_dbctl) module"]
758pub type _2_DBCTL = crate::Reg<u32, __2_DBCTL>;
759#[allow(missing_docs)]
760#[doc(hidden)]
761pub struct __2_DBCTL;
762#[doc = "`read()` method returns [_2_dbctl::R](_2_dbctl::R) reader structure"]
763impl crate::Readable for _2_DBCTL {}
764#[doc = "`write(|w| ..)` method takes [_2_dbctl::W](_2_dbctl::W) writer structure"]
765impl crate::Writable for _2_DBCTL {}
766#[doc = "PWM2 Dead-Band Control"]
767pub mod _2_dbctl;
768#[doc = "PWM2 Dead-Band Rising-Edge Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_dbrise](_2_dbrise) module"]
769pub type _2_DBRISE = crate::Reg<u32, __2_DBRISE>;
770#[allow(missing_docs)]
771#[doc(hidden)]
772pub struct __2_DBRISE;
773#[doc = "`read()` method returns [_2_dbrise::R](_2_dbrise::R) reader structure"]
774impl crate::Readable for _2_DBRISE {}
775#[doc = "`write(|w| ..)` method takes [_2_dbrise::W](_2_dbrise::W) writer structure"]
776impl crate::Writable for _2_DBRISE {}
777#[doc = "PWM2 Dead-Band Rising-Edge Delay"]
778pub mod _2_dbrise;
779#[doc = "PWM2 Dead-Band Falling-Edge-Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_dbfall](_2_dbfall) module"]
780pub type _2_DBFALL = crate::Reg<u32, __2_DBFALL>;
781#[allow(missing_docs)]
782#[doc(hidden)]
783pub struct __2_DBFALL;
784#[doc = "`read()` method returns [_2_dbfall::R](_2_dbfall::R) reader structure"]
785impl crate::Readable for _2_DBFALL {}
786#[doc = "`write(|w| ..)` method takes [_2_dbfall::W](_2_dbfall::W) writer structure"]
787impl crate::Writable for _2_DBFALL {}
788#[doc = "PWM2 Dead-Band Falling-Edge-Delay"]
789pub mod _2_dbfall;
790#[doc = "PWM2 Fault Source 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_fltsrc0](_2_fltsrc0) module"]
791pub type _2_FLTSRC0 = crate::Reg<u32, __2_FLTSRC0>;
792#[allow(missing_docs)]
793#[doc(hidden)]
794pub struct __2_FLTSRC0;
795#[doc = "`read()` method returns [_2_fltsrc0::R](_2_fltsrc0::R) reader structure"]
796impl crate::Readable for _2_FLTSRC0 {}
797#[doc = "`write(|w| ..)` method takes [_2_fltsrc0::W](_2_fltsrc0::W) writer structure"]
798impl crate::Writable for _2_FLTSRC0 {}
799#[doc = "PWM2 Fault Source 0"]
800pub mod _2_fltsrc0;
801#[doc = "PWM2 Fault Source 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_fltsrc1](_2_fltsrc1) module"]
802pub type _2_FLTSRC1 = crate::Reg<u32, __2_FLTSRC1>;
803#[allow(missing_docs)]
804#[doc(hidden)]
805pub struct __2_FLTSRC1;
806#[doc = "`read()` method returns [_2_fltsrc1::R](_2_fltsrc1::R) reader structure"]
807impl crate::Readable for _2_FLTSRC1 {}
808#[doc = "`write(|w| ..)` method takes [_2_fltsrc1::W](_2_fltsrc1::W) writer structure"]
809impl crate::Writable for _2_FLTSRC1 {}
810#[doc = "PWM2 Fault Source 1"]
811pub mod _2_fltsrc1;
812#[doc = "PWM2 Minimum Fault Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_minfltper](_2_minfltper) module"]
813pub type _2_MINFLTPER = crate::Reg<u32, __2_MINFLTPER>;
814#[allow(missing_docs)]
815#[doc(hidden)]
816pub struct __2_MINFLTPER;
817#[doc = "`read()` method returns [_2_minfltper::R](_2_minfltper::R) reader structure"]
818impl crate::Readable for _2_MINFLTPER {}
819#[doc = "`write(|w| ..)` method takes [_2_minfltper::W](_2_minfltper::W) writer structure"]
820impl crate::Writable for _2_MINFLTPER {}
821#[doc = "PWM2 Minimum Fault Period"]
822pub mod _2_minfltper;
823#[doc = "PWM3 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_ctl](_3_ctl) module"]
824pub type _3_CTL = crate::Reg<u32, __3_CTL>;
825#[allow(missing_docs)]
826#[doc(hidden)]
827pub struct __3_CTL;
828#[doc = "`read()` method returns [_3_ctl::R](_3_ctl::R) reader structure"]
829impl crate::Readable for _3_CTL {}
830#[doc = "`write(|w| ..)` method takes [_3_ctl::W](_3_ctl::W) writer structure"]
831impl crate::Writable for _3_CTL {}
832#[doc = "PWM3 Control"]
833pub mod _3_ctl;
834#[doc = "PWM3 Interrupt and Trigger Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_inten](_3_inten) module"]
835pub type _3_INTEN = crate::Reg<u32, __3_INTEN>;
836#[allow(missing_docs)]
837#[doc(hidden)]
838pub struct __3_INTEN;
839#[doc = "`read()` method returns [_3_inten::R](_3_inten::R) reader structure"]
840impl crate::Readable for _3_INTEN {}
841#[doc = "`write(|w| ..)` method takes [_3_inten::W](_3_inten::W) writer structure"]
842impl crate::Writable for _3_INTEN {}
843#[doc = "PWM3 Interrupt and Trigger Enable"]
844pub mod _3_inten;
845#[doc = "PWM3 Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_ris](_3_ris) module"]
846pub type _3_RIS = crate::Reg<u32, __3_RIS>;
847#[allow(missing_docs)]
848#[doc(hidden)]
849pub struct __3_RIS;
850#[doc = "`read()` method returns [_3_ris::R](_3_ris::R) reader structure"]
851impl crate::Readable for _3_RIS {}
852#[doc = "PWM3 Raw Interrupt Status"]
853pub mod _3_ris;
854#[doc = "PWM3 Interrupt Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_isc](_3_isc) module"]
855pub type _3_ISC = crate::Reg<u32, __3_ISC>;
856#[allow(missing_docs)]
857#[doc(hidden)]
858pub struct __3_ISC;
859#[doc = "`read()` method returns [_3_isc::R](_3_isc::R) reader structure"]
860impl crate::Readable for _3_ISC {}
861#[doc = "`write(|w| ..)` method takes [_3_isc::W](_3_isc::W) writer structure"]
862impl crate::Writable for _3_ISC {}
863#[doc = "PWM3 Interrupt Status and Clear"]
864pub mod _3_isc;
865#[doc = "PWM3 Load\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_load](_3_load) module"]
866pub type _3_LOAD = crate::Reg<u32, __3_LOAD>;
867#[allow(missing_docs)]
868#[doc(hidden)]
869pub struct __3_LOAD;
870#[doc = "`read()` method returns [_3_load::R](_3_load::R) reader structure"]
871impl crate::Readable for _3_LOAD {}
872#[doc = "`write(|w| ..)` method takes [_3_load::W](_3_load::W) writer structure"]
873impl crate::Writable for _3_LOAD {}
874#[doc = "PWM3 Load"]
875pub mod _3_load;
876#[doc = "PWM3 Counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_count](_3_count) module"]
877pub type _3_COUNT = crate::Reg<u32, __3_COUNT>;
878#[allow(missing_docs)]
879#[doc(hidden)]
880pub struct __3_COUNT;
881#[doc = "`read()` method returns [_3_count::R](_3_count::R) reader structure"]
882impl crate::Readable for _3_COUNT {}
883#[doc = "PWM3 Counter"]
884pub mod _3_count;
885#[doc = "PWM3 Compare A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_cmpa](_3_cmpa) module"]
886pub type _3_CMPA = crate::Reg<u32, __3_CMPA>;
887#[allow(missing_docs)]
888#[doc(hidden)]
889pub struct __3_CMPA;
890#[doc = "`read()` method returns [_3_cmpa::R](_3_cmpa::R) reader structure"]
891impl crate::Readable for _3_CMPA {}
892#[doc = "`write(|w| ..)` method takes [_3_cmpa::W](_3_cmpa::W) writer structure"]
893impl crate::Writable for _3_CMPA {}
894#[doc = "PWM3 Compare A"]
895pub mod _3_cmpa;
896#[doc = "PWM3 Compare B\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_cmpb](_3_cmpb) module"]
897pub type _3_CMPB = crate::Reg<u32, __3_CMPB>;
898#[allow(missing_docs)]
899#[doc(hidden)]
900pub struct __3_CMPB;
901#[doc = "`read()` method returns [_3_cmpb::R](_3_cmpb::R) reader structure"]
902impl crate::Readable for _3_CMPB {}
903#[doc = "`write(|w| ..)` method takes [_3_cmpb::W](_3_cmpb::W) writer structure"]
904impl crate::Writable for _3_CMPB {}
905#[doc = "PWM3 Compare B"]
906pub mod _3_cmpb;
907#[doc = "PWM3 Generator A Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_gena](_3_gena) module"]
908pub type _3_GENA = crate::Reg<u32, __3_GENA>;
909#[allow(missing_docs)]
910#[doc(hidden)]
911pub struct __3_GENA;
912#[doc = "`read()` method returns [_3_gena::R](_3_gena::R) reader structure"]
913impl crate::Readable for _3_GENA {}
914#[doc = "`write(|w| ..)` method takes [_3_gena::W](_3_gena::W) writer structure"]
915impl crate::Writable for _3_GENA {}
916#[doc = "PWM3 Generator A Control"]
917pub mod _3_gena;
918#[doc = "PWM3 Generator B Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_genb](_3_genb) module"]
919pub type _3_GENB = crate::Reg<u32, __3_GENB>;
920#[allow(missing_docs)]
921#[doc(hidden)]
922pub struct __3_GENB;
923#[doc = "`read()` method returns [_3_genb::R](_3_genb::R) reader structure"]
924impl crate::Readable for _3_GENB {}
925#[doc = "`write(|w| ..)` method takes [_3_genb::W](_3_genb::W) writer structure"]
926impl crate::Writable for _3_GENB {}
927#[doc = "PWM3 Generator B Control"]
928pub mod _3_genb;
929#[doc = "PWM3 Dead-Band Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_dbctl](_3_dbctl) module"]
930pub type _3_DBCTL = crate::Reg<u32, __3_DBCTL>;
931#[allow(missing_docs)]
932#[doc(hidden)]
933pub struct __3_DBCTL;
934#[doc = "`read()` method returns [_3_dbctl::R](_3_dbctl::R) reader structure"]
935impl crate::Readable for _3_DBCTL {}
936#[doc = "`write(|w| ..)` method takes [_3_dbctl::W](_3_dbctl::W) writer structure"]
937impl crate::Writable for _3_DBCTL {}
938#[doc = "PWM3 Dead-Band Control"]
939pub mod _3_dbctl;
940#[doc = "PWM3 Dead-Band Rising-Edge Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_dbrise](_3_dbrise) module"]
941pub type _3_DBRISE = crate::Reg<u32, __3_DBRISE>;
942#[allow(missing_docs)]
943#[doc(hidden)]
944pub struct __3_DBRISE;
945#[doc = "`read()` method returns [_3_dbrise::R](_3_dbrise::R) reader structure"]
946impl crate::Readable for _3_DBRISE {}
947#[doc = "`write(|w| ..)` method takes [_3_dbrise::W](_3_dbrise::W) writer structure"]
948impl crate::Writable for _3_DBRISE {}
949#[doc = "PWM3 Dead-Band Rising-Edge Delay"]
950pub mod _3_dbrise;
951#[doc = "PWM3 Dead-Band Falling-Edge-Delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_dbfall](_3_dbfall) module"]
952pub type _3_DBFALL = crate::Reg<u32, __3_DBFALL>;
953#[allow(missing_docs)]
954#[doc(hidden)]
955pub struct __3_DBFALL;
956#[doc = "`read()` method returns [_3_dbfall::R](_3_dbfall::R) reader structure"]
957impl crate::Readable for _3_DBFALL {}
958#[doc = "`write(|w| ..)` method takes [_3_dbfall::W](_3_dbfall::W) writer structure"]
959impl crate::Writable for _3_DBFALL {}
960#[doc = "PWM3 Dead-Band Falling-Edge-Delay"]
961pub mod _3_dbfall;
962#[doc = "PWM3 Fault Source 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_fltsrc0](_3_fltsrc0) module"]
963pub type _3_FLTSRC0 = crate::Reg<u32, __3_FLTSRC0>;
964#[allow(missing_docs)]
965#[doc(hidden)]
966pub struct __3_FLTSRC0;
967#[doc = "`read()` method returns [_3_fltsrc0::R](_3_fltsrc0::R) reader structure"]
968impl crate::Readable for _3_FLTSRC0 {}
969#[doc = "`write(|w| ..)` method takes [_3_fltsrc0::W](_3_fltsrc0::W) writer structure"]
970impl crate::Writable for _3_FLTSRC0 {}
971#[doc = "PWM3 Fault Source 0"]
972pub mod _3_fltsrc0;
973#[doc = "PWM3 Fault Source 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_fltsrc1](_3_fltsrc1) module"]
974pub type _3_FLTSRC1 = crate::Reg<u32, __3_FLTSRC1>;
975#[allow(missing_docs)]
976#[doc(hidden)]
977pub struct __3_FLTSRC1;
978#[doc = "`read()` method returns [_3_fltsrc1::R](_3_fltsrc1::R) reader structure"]
979impl crate::Readable for _3_FLTSRC1 {}
980#[doc = "`write(|w| ..)` method takes [_3_fltsrc1::W](_3_fltsrc1::W) writer structure"]
981impl crate::Writable for _3_FLTSRC1 {}
982#[doc = "PWM3 Fault Source 1"]
983pub mod _3_fltsrc1;
984#[doc = "PWM3 Minimum Fault Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_minfltper](_3_minfltper) module"]
985pub type _3_MINFLTPER = crate::Reg<u32, __3_MINFLTPER>;
986#[allow(missing_docs)]
987#[doc(hidden)]
988pub struct __3_MINFLTPER;
989#[doc = "`read()` method returns [_3_minfltper::R](_3_minfltper::R) reader structure"]
990impl crate::Readable for _3_MINFLTPER {}
991#[doc = "`write(|w| ..)` method takes [_3_minfltper::W](_3_minfltper::W) writer structure"]
992impl crate::Writable for _3_MINFLTPER {}
993#[doc = "PWM3 Minimum Fault Period"]
994pub mod _3_minfltper;
995#[doc = "PWM0 Fault Pin Logic Sense\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_fltsen](_0_fltsen) module"]
996pub type _0_FLTSEN = crate::Reg<u32, __0_FLTSEN>;
997#[allow(missing_docs)]
998#[doc(hidden)]
999pub struct __0_FLTSEN;
1000#[doc = "`read()` method returns [_0_fltsen::R](_0_fltsen::R) reader structure"]
1001impl crate::Readable for _0_FLTSEN {}
1002#[doc = "`write(|w| ..)` method takes [_0_fltsen::W](_0_fltsen::W) writer structure"]
1003impl crate::Writable for _0_FLTSEN {}
1004#[doc = "PWM0 Fault Pin Logic Sense"]
1005pub mod _0_fltsen;
1006#[doc = "PWM0 Fault Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_fltstat0](_0_fltstat0) module"]
1007pub type _0_FLTSTAT0 = crate::Reg<u32, __0_FLTSTAT0>;
1008#[allow(missing_docs)]
1009#[doc(hidden)]
1010pub struct __0_FLTSTAT0;
1011#[doc = "`read()` method returns [_0_fltstat0::R](_0_fltstat0::R) reader structure"]
1012impl crate::Readable for _0_FLTSTAT0 {}
1013#[doc = "`write(|w| ..)` method takes [_0_fltstat0::W](_0_fltstat0::W) writer structure"]
1014impl crate::Writable for _0_FLTSTAT0 {}
1015#[doc = "PWM0 Fault Status 0"]
1016pub mod _0_fltstat0;
1017#[doc = "PWM0 Fault Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_0_fltstat1](_0_fltstat1) module"]
1018pub type _0_FLTSTAT1 = crate::Reg<u32, __0_FLTSTAT1>;
1019#[allow(missing_docs)]
1020#[doc(hidden)]
1021pub struct __0_FLTSTAT1;
1022#[doc = "`read()` method returns [_0_fltstat1::R](_0_fltstat1::R) reader structure"]
1023impl crate::Readable for _0_FLTSTAT1 {}
1024#[doc = "`write(|w| ..)` method takes [_0_fltstat1::W](_0_fltstat1::W) writer structure"]
1025impl crate::Writable for _0_FLTSTAT1 {}
1026#[doc = "PWM0 Fault Status 1"]
1027pub mod _0_fltstat1;
1028#[doc = "PWM1 Fault Pin Logic Sense\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_fltsen](_1_fltsen) module"]
1029pub type _1_FLTSEN = crate::Reg<u32, __1_FLTSEN>;
1030#[allow(missing_docs)]
1031#[doc(hidden)]
1032pub struct __1_FLTSEN;
1033#[doc = "`read()` method returns [_1_fltsen::R](_1_fltsen::R) reader structure"]
1034impl crate::Readable for _1_FLTSEN {}
1035#[doc = "`write(|w| ..)` method takes [_1_fltsen::W](_1_fltsen::W) writer structure"]
1036impl crate::Writable for _1_FLTSEN {}
1037#[doc = "PWM1 Fault Pin Logic Sense"]
1038pub mod _1_fltsen;
1039#[doc = "PWM1 Fault Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_fltstat0](_1_fltstat0) module"]
1040pub type _1_FLTSTAT0 = crate::Reg<u32, __1_FLTSTAT0>;
1041#[allow(missing_docs)]
1042#[doc(hidden)]
1043pub struct __1_FLTSTAT0;
1044#[doc = "`read()` method returns [_1_fltstat0::R](_1_fltstat0::R) reader structure"]
1045impl crate::Readable for _1_FLTSTAT0 {}
1046#[doc = "`write(|w| ..)` method takes [_1_fltstat0::W](_1_fltstat0::W) writer structure"]
1047impl crate::Writable for _1_FLTSTAT0 {}
1048#[doc = "PWM1 Fault Status 0"]
1049pub mod _1_fltstat0;
1050#[doc = "PWM1 Fault Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_1_fltstat1](_1_fltstat1) module"]
1051pub type _1_FLTSTAT1 = crate::Reg<u32, __1_FLTSTAT1>;
1052#[allow(missing_docs)]
1053#[doc(hidden)]
1054pub struct __1_FLTSTAT1;
1055#[doc = "`read()` method returns [_1_fltstat1::R](_1_fltstat1::R) reader structure"]
1056impl crate::Readable for _1_FLTSTAT1 {}
1057#[doc = "`write(|w| ..)` method takes [_1_fltstat1::W](_1_fltstat1::W) writer structure"]
1058impl crate::Writable for _1_FLTSTAT1 {}
1059#[doc = "PWM1 Fault Status 1"]
1060pub mod _1_fltstat1;
1061#[doc = "PWM2 Fault Pin Logic Sense\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_fltsen](_2_fltsen) module"]
1062pub type _2_FLTSEN = crate::Reg<u32, __2_FLTSEN>;
1063#[allow(missing_docs)]
1064#[doc(hidden)]
1065pub struct __2_FLTSEN;
1066#[doc = "`read()` method returns [_2_fltsen::R](_2_fltsen::R) reader structure"]
1067impl crate::Readable for _2_FLTSEN {}
1068#[doc = "`write(|w| ..)` method takes [_2_fltsen::W](_2_fltsen::W) writer structure"]
1069impl crate::Writable for _2_FLTSEN {}
1070#[doc = "PWM2 Fault Pin Logic Sense"]
1071pub mod _2_fltsen;
1072#[doc = "PWM2 Fault Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_fltstat0](_2_fltstat0) module"]
1073pub type _2_FLTSTAT0 = crate::Reg<u32, __2_FLTSTAT0>;
1074#[allow(missing_docs)]
1075#[doc(hidden)]
1076pub struct __2_FLTSTAT0;
1077#[doc = "`read()` method returns [_2_fltstat0::R](_2_fltstat0::R) reader structure"]
1078impl crate::Readable for _2_FLTSTAT0 {}
1079#[doc = "`write(|w| ..)` method takes [_2_fltstat0::W](_2_fltstat0::W) writer structure"]
1080impl crate::Writable for _2_FLTSTAT0 {}
1081#[doc = "PWM2 Fault Status 0"]
1082pub mod _2_fltstat0;
1083#[doc = "PWM2 Fault Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_2_fltstat1](_2_fltstat1) module"]
1084pub type _2_FLTSTAT1 = crate::Reg<u32, __2_FLTSTAT1>;
1085#[allow(missing_docs)]
1086#[doc(hidden)]
1087pub struct __2_FLTSTAT1;
1088#[doc = "`read()` method returns [_2_fltstat1::R](_2_fltstat1::R) reader structure"]
1089impl crate::Readable for _2_FLTSTAT1 {}
1090#[doc = "`write(|w| ..)` method takes [_2_fltstat1::W](_2_fltstat1::W) writer structure"]
1091impl crate::Writable for _2_FLTSTAT1 {}
1092#[doc = "PWM2 Fault Status 1"]
1093pub mod _2_fltstat1;
1094#[doc = "PWM3 Fault Pin Logic Sense\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_fltsen](_3_fltsen) module"]
1095pub type _3_FLTSEN = crate::Reg<u32, __3_FLTSEN>;
1096#[allow(missing_docs)]
1097#[doc(hidden)]
1098pub struct __3_FLTSEN;
1099#[doc = "`read()` method returns [_3_fltsen::R](_3_fltsen::R) reader structure"]
1100impl crate::Readable for _3_FLTSEN {}
1101#[doc = "`write(|w| ..)` method takes [_3_fltsen::W](_3_fltsen::W) writer structure"]
1102impl crate::Writable for _3_FLTSEN {}
1103#[doc = "PWM3 Fault Pin Logic Sense"]
1104pub mod _3_fltsen;
1105#[doc = "PWM3 Fault Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_fltstat0](_3_fltstat0) module"]
1106pub type _3_FLTSTAT0 = crate::Reg<u32, __3_FLTSTAT0>;
1107#[allow(missing_docs)]
1108#[doc(hidden)]
1109pub struct __3_FLTSTAT0;
1110#[doc = "`read()` method returns [_3_fltstat0::R](_3_fltstat0::R) reader structure"]
1111impl crate::Readable for _3_FLTSTAT0 {}
1112#[doc = "`write(|w| ..)` method takes [_3_fltstat0::W](_3_fltstat0::W) writer structure"]
1113impl crate::Writable for _3_FLTSTAT0 {}
1114#[doc = "PWM3 Fault Status 0"]
1115pub mod _3_fltstat0;
1116#[doc = "PWM3 Fault Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [_3_fltstat1](_3_fltstat1) module"]
1117pub type _3_FLTSTAT1 = crate::Reg<u32, __3_FLTSTAT1>;
1118#[allow(missing_docs)]
1119#[doc(hidden)]
1120pub struct __3_FLTSTAT1;
1121#[doc = "`read()` method returns [_3_fltstat1::R](_3_fltstat1::R) reader structure"]
1122impl crate::Readable for _3_FLTSTAT1 {}
1123#[doc = "`write(|w| ..)` method takes [_3_fltstat1::W](_3_fltstat1::W) writer structure"]
1124impl crate::Writable for _3_FLTSTAT1 {}
1125#[doc = "PWM3 Fault Status 1"]
1126pub mod _3_fltstat1;
1127#[doc = "PWM Peripheral Properties\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pp](pp) module"]
1128pub type PP = crate::Reg<u32, _PP>;
1129#[allow(missing_docs)]
1130#[doc(hidden)]
1131pub struct _PP;
1132#[doc = "`read()` method returns [pp::R](pp::R) reader structure"]
1133impl crate::Readable for PP {}
1134#[doc = "PWM Peripheral Properties"]
1135pub mod pp;
1136#[doc = "PWM Clock Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](cc) module"]
1137pub type CC = crate::Reg<u32, _CC>;
1138#[allow(missing_docs)]
1139#[doc(hidden)]
1140pub struct _CC;
1141#[doc = "`read()` method returns [cc::R](cc::R) reader structure"]
1142impl crate::Readable for CC {}
1143#[doc = "`write(|w| ..)` method takes [cc::W](cc::W) writer structure"]
1144impl crate::Writable for CC {}
1145#[doc = "PWM Clock Configuration"]
1146pub mod cc;