Struct tm4c123x::udma::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 23 fields
pub stat: STAT,
pub cfg: CFG,
pub ctlbase: CTLBASE,
pub altbase: ALTBASE,
pub waitstat: WAITSTAT,
pub swreq: SWREQ,
pub useburstset: USEBURSTSET,
pub useburstclr: USEBURSTCLR,
pub reqmaskset: REQMASKSET,
pub reqmaskclr: REQMASKCLR,
pub enaset: ENASET,
pub enaclr: ENACLR,
pub altset: ALTSET,
pub altclr: ALTCLR,
pub prioset: PRIOSET,
pub prioclr: PRIOCLR,
pub errclr: ERRCLR,
pub chasgn: CHASGN,
pub chis: CHIS,
pub chmap0: CHMAP0,
pub chmap1: CHMAP1,
pub chmap2: CHMAP2,
pub chmap3: CHMAP3,
/* private fields */
}
Expand description
Register block
Fields§
§stat: STAT
0x00 - DMA Status
cfg: CFG
0x04 - DMA Configuration
ctlbase: CTLBASE
0x08 - DMA Channel Control Base Pointer
altbase: ALTBASE
0x0c - DMA Alternate Channel Control Base Pointer
waitstat: WAITSTAT
0x10 - DMA Channel Wait-on-Request Status
swreq: SWREQ
0x14 - DMA Channel Software Request
useburstset: USEBURSTSET
0x18 - DMA Channel Useburst Set
useburstclr: USEBURSTCLR
0x1c - DMA Channel Useburst Clear
reqmaskset: REQMASKSET
0x20 - DMA Channel Request Mask Set
reqmaskclr: REQMASKCLR
0x24 - DMA Channel Request Mask Clear
enaset: ENASET
0x28 - DMA Channel Enable Set
enaclr: ENACLR
0x2c - DMA Channel Enable Clear
altset: ALTSET
0x30 - DMA Channel Primary Alternate Set
altclr: ALTCLR
0x34 - DMA Channel Primary Alternate Clear
prioset: PRIOSET
0x38 - DMA Channel Priority Set
prioclr: PRIOCLR
0x3c - DMA Channel Priority Clear
errclr: ERRCLR
0x4c - DMA Bus Error Clear
chasgn: CHASGN
0x500 - DMA Channel Assignment
chis: CHIS
0x504 - DMA Channel Interrupt Status
chmap0: CHMAP0
0x510 - DMA Channel Map Select 0
chmap1: CHMAP1
0x514 - DMA Channel Map Select 1
chmap2: CHMAP2
0x518 - DMA Channel Map Select 2
chmap3: CHMAP3
0x51c - DMA Channel Map Select 3