tinyboot_ch32_hal/rcc/
v0.rs

1pub fn enable_gpio(port_index: usize) {
2    // IOPxEN bits are consecutive starting at bit 2: IOPA=2, IOPB=3, IOPC=4, IOPD=5.
3    ch32_metapac::RCC
4        .apb2pcenr()
5        .modify(|w| w.0 |= 1 << (2 + port_index));
6}
7
8pub fn enable_afio() {
9    ch32_metapac::RCC.apb2pcenr().modify(|w| w.set_afioen(true));
10}
11
12const USART1EN: u32 = 1 << 14;
13
14/// APB2 enable bit for USART `n`, or 0 if not on APB2.
15pub const fn usart_apb2_bit(n: u8) -> u32 {
16    match n {
17        1 => USART1EN,
18        _ => 0,
19    }
20}
21
22/// Enable USART `n` clock on whichever bus it lives on.
23pub fn enable_usart(n: u8) {
24    let bit = usart_apb2_bit(n);
25    if bit != 0 {
26        ch32_metapac::RCC.apb2pcenr().modify(|w| w.0 |= bit);
27    }
28}
29
30/// Batch-enable APB2 peripherals in a single write.
31/// Only safe at init before other peripherals are enabled.
32#[inline(always)]
33pub fn enable_apb2(bits: u32) {
34    ch32_metapac::RCC.apb2pcenr().write(|w| w.0 = bits);
35}
36
37/// Pulse-reset all APB2 peripherals (USART1, GPIO, AFIO, etc.)
38/// then disable their clocks — restores power-on default state.
39#[inline(always)]
40pub fn reset_apb2() {
41    let rcc = ch32_metapac::RCC;
42    let enabled = rcc.apb2pcenr().read().0;
43    rcc.apb2prstr().write(|w| w.0 = enabled);
44    rcc.apb2prstr().write(|w| w.0 = 0);
45    rcc.apb2pcenr().write(|w| w.0 = 0);
46}
tinyboot_ch32_hal/rcc/v0.rs

tinyboot_ch32_hal/rcc/
v0.rs
