tfhe_hpu_backend/interface/rtl/
runtime.rs

1//!
2//! Define structure and way to read them from register for all the
3//! Hpu runtime information
4use super::*;
5
6#[derive(Debug, Default)]
7pub struct InfoPePbs {
8    /// Bpip used
9    bpip_use: bool,
10    /// Bpip use opportunism
11    bpip_use_opportunism: bool,
12    /// Bpip timeout
13    bpip_timeout: u32,
14
15    /// PBS current BR-loop
16    br_loop: u16,
17    /// PBS current BR-loop parity
18    br_loop_c: u8,
19
20    /// KS current KS-loop
21    ks_loop: u16,
22    /// KS current BR-loop parity
23    ks_loop_c: u8,
24
25    /// pe_pbs pool_rp
26    pool_rp: u8,
27    /// pe_pbs pool_wp
28    pool_wp: u8,
29    /// pe_pbs ldg_pt
30    ldg_pt: u8,
31    /// pe_pbs ldb_pt
32    ldb_pt: u8,
33
34    /// pe_pbs ks_in_rp
35    ks_in_rp: u8,
36    /// pe_pbs ks_in_wp
37    ks_in_wp: u8,
38    /// pe_pbs ks_out_rp
39    ks_out_rp: u8,
40    /// pe_pbs ks_out_wp
41    ks_out_wp: u8,
42    /// pe_pbs pbs_in_rp
43    pbs_in_rp: u8,
44    /// pe_pbs pbs_in_wp
45    pbs_in_wp: u8,
46
47    /// pe_pbs IPIP flush last pbs_in_loop
48    ipip_flush_last_pbs_in_loop: u16,
49    /// pe_pbs BPIP batch that waits the trigger counter (Could be reset by user)
50    seq_bpip_waiting_batch_cnt: u32,
51    /// pe_pbs Count batch with filled with a given number of CT (Could be reset by user)
52    seq_bpip_batch_filling_cnt: [u32; 16],
53
54    /// pe_pbs ack counter (Could be reset by user)
55    seq_ld_ack_cnt: u32,
56
57    /// pe_pbs not full batch CMUX counter (Could be reset by user)
58    seq_cmux_not_full_batch_cnt: u32,
59
60    /// pe_pbs BPIP batch counter (Could be reset by user)
61    seq_bpip_batch_cnt: u32,
62    /// pe_pbs BPIP batch triggered with a flush counter (Could be reset by user)
63    seq_bpip_batch_flush_cnt: u32,
64    /// pe_pbs BPIP batch triggered with a timeout counter (Could be reset by user)
65    seq_bpip_batch_timeout_cnt: u32,
66
67    /// pe_pbs IPIP flush CMUX counter (Could be reset by user)
68    seq_ipip_flush_cnt: u32,
69    /// pe_pbs load BLWE reception max duration (Could be reset by user)
70    ldb_rcp_dur: u32,
71    /// pe_pbs load GLWE request max duration (Could be reset by user)
72    ldg_req_dur: u32,
73    /// pe_pbs load GLWE reception max duration (Could be reset by user)
74    ldg_rcp_dur: u32,
75    /// pe_pbs MMACC SXT reception duration (Could be reset by user)
76    mmacc_sxt_rcp_dur: u32,
77
78    /// pe_pbs MMACC SXT request duration (Could be reset by user)
79    mmacc_sxt_req_dur: u32,
80    /// pe_pbs MMACC SXT command without b duration (Could be reset by user)
81    mmacc_sxt_cmd_wait_b_dur: u32,
82
83    /// PEP input instruction counter (Could be reset by user)
84    pep_inst_cnt: u32,
85    /// PEP instruction acknowledge counter (Could be reset by user)
86    pep_ack_cnt: u32,
87
88    /// pe_pbs load BSK slice reception max duration (Could be reset by user)
89    load_bsk_rcp_dur: [u32; 16],
90    /// pe_pbs load KSK slice reception max duration (Could be reset by user)
91    load_ksk_rcp_dur: [u32; 16],
92
93    /// pe_pbs bsk_if req_br_loop_rp
94    bskif_req_br_loop_rp: u16,
95    /// pe_pbs bsk_if req_br_loop_wp
96    bskif_req_br_loop_wp: u16,
97    /// pe_pbs bsk_if req_prf_br_loop
98    bskif_req_prf_br_loop: u16,
99    /// pe_pbs bsk_if req_parity
100    bskif_req_parity: u8,
101    /// pe_pbs bsk_if req_assigned
102    bskif_req_assigned: u8,
103}
104
105impl FromRtl for InfoPePbs {
106    fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
107        // Info structure have method to update
108        // Instead of redefine parsing here, use a default construct and update methods
109        let mut infos = Self::default();
110        infos.update(ffi_hw, regmap);
111        infos
112    }
113}
114
115/// Add facilities once created to update/reset some fields
116impl InfoPePbs {
117    pub fn update(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
118        self.update_bpip(ffi_hw, regmap);
119        self.update_loop(ffi_hw, regmap);
120        self.update_pointer0(ffi_hw, regmap);
121        self.update_pointer1(ffi_hw, regmap);
122        self.update_pointer2(ffi_hw, regmap);
123        self.update_seq_bpip_waiting_batch_cnt(ffi_hw, regmap);
124        self.update_seq_bpip_batch_filling_cnt(ffi_hw, regmap);
125        self.update_seq_ld_ack_cnt(ffi_hw, regmap);
126        self.update_seq_cmux_not_full_batch_cnt(ffi_hw, regmap);
127        self.update_seq_bpip_batch_cnt(ffi_hw, regmap);
128        self.update_seq_bpip_batch_flush_cnt(ffi_hw, regmap);
129        self.update_seq_bpip_batch_timeout_cnt(ffi_hw, regmap);
130        self.update_seq_ipip_flush_cnt(ffi_hw, regmap);
131        self.update_ldb_rcp_dur(ffi_hw, regmap);
132        self.update_ldg_req_dur(ffi_hw, regmap);
133        self.update_ldg_rcp_dur(ffi_hw, regmap);
134        self.update_mmacc_sxt_rcp_dur(ffi_hw, regmap);
135        self.update_mmacc_sxt_req_dur(ffi_hw, regmap);
136        self.update_mmacc_sxt_cmd_wait_b_dur(ffi_hw, regmap);
137        self.update_pep_inst_cnt(ffi_hw, regmap);
138        self.update_pep_ack_cnt(ffi_hw, regmap);
139        self.update_load_bsk_rcp_dur(ffi_hw, regmap);
140        self.update_load_ksk_rcp_dur(ffi_hw, regmap);
141        self.update_pep_bskif_req_info_0(ffi_hw, regmap);
142        self.update_pep_bskif_req_info_1(ffi_hw, regmap);
143    }
144
145    pub fn update_bpip(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
146        let reg_use = regmap
147            .register()
148            .get("bpip::use")
149            .expect("Unknown register, check regmap definition");
150        let val = ffi_hw.read_reg(*reg_use.offset() as u64);
151        let fields = reg_use.as_field(val);
152        self.bpip_use = *fields.get("use_bpip").expect("Unknown field") == 1;
153        self.bpip_use_opportunism = *fields
154            .get("use_opportunism")
155            .expect("Unknown field opportunism")
156            == 1;
157        let reg_timeout = regmap
158            .register()
159            .get("bpip::timeout")
160            .expect("Unknown register, check regmap definition");
161        self.bpip_timeout = ffi_hw.read_reg(*reg_timeout.offset() as u64);
162    }
163
164    pub fn update_loop(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
165        let reg = regmap
166            .register()
167            .get("runtime_1in3::pep_cmux_loop")
168            .expect("Unknown register, check regmap definition");
169        let val = ffi_hw.read_reg(*reg.offset() as u64);
170        let fields = reg.as_field(val);
171        self.br_loop = *fields.get("br_loop").expect("Unknown field") as u16;
172        self.br_loop_c = *fields.get("br_loop_c").expect("Unknown field") as u8;
173        self.ks_loop = *fields.get("ks_loop").expect("Unknown field") as u16;
174        self.ks_loop_c = *fields.get("ks_loop_c").expect("Unknown field") as u8;
175    }
176    pub fn update_pointer0(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
177        let reg = regmap
178            .register()
179            .get("runtime_1in3::pep_pointer_0")
180            .expect("Unknown register, check regmap definition");
181        let val = ffi_hw.read_reg(*reg.offset() as u64);
182        let fields = reg.as_field(val);
183        self.pool_rp = *fields.get("pool_rp").expect("Unknown field") as u8;
184        self.pool_wp = *fields.get("pool_wp").expect("Unknown field") as u8;
185        self.ldg_pt = *fields.get("ldg_pt").expect("Unknown field") as u8;
186        self.ldb_pt = *fields.get("ldb_pt").expect("Unknown field") as u8;
187    }
188
189    pub fn update_pointer1(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
190        let reg = regmap
191            .register()
192            .get("runtime_1in3::pep_pointer_1")
193            .expect("Unknown register, check regmap definition");
194        let val = ffi_hw.read_reg(*reg.offset() as u64);
195        let fields = reg.as_field(val);
196        self.ks_in_rp = *fields.get("ks_in_rp").expect("Unknown field") as u8;
197        self.ks_in_wp = *fields.get("ks_in_wp").expect("Unknown field") as u8;
198        self.ks_out_rp = *fields.get("ks_out_rp").expect("Unknown field") as u8;
199        self.ks_out_wp = *fields.get("ks_out_wp").expect("Unknown field") as u8;
200    }
201
202    pub fn update_pointer2(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
203        let reg = regmap
204            .register()
205            .get("runtime_1in3::pep_pointer_2")
206            .expect("Unknown register, check regmap definition");
207        let val = ffi_hw.read_reg(*reg.offset() as u64);
208        let fields = reg.as_field(val);
209        self.pbs_in_rp = *fields.get("pbs_in_rp").expect("Unknown field") as u8;
210        self.pbs_in_wp = *fields.get("pbs_in_wp").expect("Unknown field") as u8;
211        self.ipip_flush_last_pbs_in_loop = *fields
212            .get("ipip_flush_last_pbs_in_loop")
213            .expect("Unknown field") as u16;
214    }
215
216    pub fn update_seq_bpip_waiting_batch_cnt(
217        &mut self,
218        ffi_hw: &mut ffi::HpuHw,
219        regmap: &FlatRegmap,
220    ) {
221        let reg = regmap
222            .register()
223            .get("runtime_1in3::pep_seq_bpip_waiting_batch_cnt")
224            .expect("Unknown register, check regmap definition");
225        self.seq_bpip_waiting_batch_cnt = ffi_hw.read_reg(*reg.offset() as u64);
226    }
227
228    pub fn update_seq_bpip_batch_filling_cnt(
229        &mut self,
230        ffi_hw: &mut ffi::HpuHw,
231        regmap: &FlatRegmap,
232    ) {
233        (1..16).for_each(|i| {
234            let reg_name = format!("runtime_1in3::pep_seq_bpip_batch_filling_cnt_{i}");
235            let reg = regmap
236                .register()
237                .get(&reg_name)
238                .expect("Unknown register, check regmap definition");
239            self.seq_bpip_batch_filling_cnt[i] = ffi_hw.read_reg(*reg.offset() as u64)
240        });
241    }
242
243    pub fn update_seq_ld_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
244        let reg = regmap
245            .register()
246            .get("runtime_1in3::pep_seq_ld_ack_cnt")
247            .expect("Unknown register, check regmap definition");
248        self.seq_ld_ack_cnt = ffi_hw.read_reg(*reg.offset() as u64);
249    }
250
251    pub fn update_seq_cmux_not_full_batch_cnt(
252        &mut self,
253        ffi_hw: &mut ffi::HpuHw,
254        regmap: &FlatRegmap,
255    ) {
256        let reg = regmap
257            .register()
258            .get("runtime_1in3::pep_seq_cmux_not_full_batch_cnt")
259            .expect("Unknown register, check regmap definition");
260        self.seq_cmux_not_full_batch_cnt = ffi_hw.read_reg(*reg.offset() as u64);
261    }
262
263    pub fn update_seq_bpip_batch_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
264        let reg = regmap
265            .register()
266            .get("runtime_1in3::pep_seq_bpip_batch_cnt")
267            .expect("Unknown register, check regmap definition");
268        self.seq_bpip_batch_cnt = ffi_hw.read_reg(*reg.offset() as u64);
269    }
270    pub fn update_seq_bpip_batch_flush_cnt(
271        &mut self,
272        ffi_hw: &mut ffi::HpuHw,
273        regmap: &FlatRegmap,
274    ) {
275        let reg = regmap
276            .register()
277            .get("runtime_1in3::pep_seq_bpip_batch_flush_cnt")
278            .expect("Unknown register, check regmap definition");
279        self.seq_bpip_batch_flush_cnt = ffi_hw.read_reg(*reg.offset() as u64);
280    }
281    pub fn update_seq_bpip_batch_timeout_cnt(
282        &mut self,
283        ffi_hw: &mut ffi::HpuHw,
284        regmap: &FlatRegmap,
285    ) {
286        let reg = regmap
287            .register()
288            .get("runtime_1in3::pep_seq_bpip_batch_timeout_cnt")
289            .expect("Unknown register, check regmap definition");
290        self.seq_bpip_batch_timeout_cnt = ffi_hw.read_reg(*reg.offset() as u64);
291    }
292
293    pub fn update_seq_ipip_flush_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
294        let reg = regmap
295            .register()
296            .get("runtime_1in3::pep_seq_ipip_flush_cnt")
297            .expect("Unknown register, check regmap definition");
298        self.seq_ipip_flush_cnt = ffi_hw.read_reg(*reg.offset() as u64);
299    }
300
301    pub fn update_ldb_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
302        let reg = regmap
303            .register()
304            .get("runtime_1in3::pep_ldb_rcp_dur")
305            .expect("Unknown register, check regmap definition");
306        self.ldb_rcp_dur = ffi_hw.read_reg(*reg.offset() as u64);
307    }
308    pub fn update_ldg_req_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
309        let reg = regmap
310            .register()
311            .get("runtime_1in3::pep_ldg_req_dur")
312            .expect("Unknown register, check regmap definition");
313        self.ldg_req_dur = ffi_hw.read_reg(*reg.offset() as u64);
314    }
315    pub fn update_ldg_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
316        let reg = regmap
317            .register()
318            .get("runtime_1in3::pep_ldg_rcp_dur")
319            .expect("Unknown register, check regmap definition");
320        self.ldg_rcp_dur = ffi_hw.read_reg(*reg.offset() as u64);
321    }
322    pub fn update_mmacc_sxt_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
323        let reg = regmap
324            .register()
325            .get("runtime_1in3::pep_mmacc_sxt_rcp_dur")
326            .expect("Unknown register, check regmap definition");
327        self.mmacc_sxt_rcp_dur = ffi_hw.read_reg(*reg.offset() as u64);
328    }
329    pub fn update_mmacc_sxt_req_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
330        let reg = regmap
331            .register()
332            .get("runtime_1in3::pep_mmacc_sxt_req_dur")
333            .expect("Unknown register, check regmap definition");
334        self.mmacc_sxt_req_dur = ffi_hw.read_reg(*reg.offset() as u64);
335    }
336    pub fn update_mmacc_sxt_cmd_wait_b_dur(
337        &mut self,
338        ffi_hw: &mut ffi::HpuHw,
339        regmap: &FlatRegmap,
340    ) {
341        let reg = regmap
342            .register()
343            .get("runtime_1in3::pep_mmacc_sxt_cmd_wait_b_dur")
344            .expect("Unknown register, check regmap definition");
345        self.mmacc_sxt_cmd_wait_b_dur = ffi_hw.read_reg(*reg.offset() as u64);
346    }
347
348    pub fn update_pep_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
349        let reg = regmap
350            .register()
351            .get("runtime_1in3::pep_inst_cnt")
352            .expect("Unknown register, check regmap definition");
353        self.pep_inst_cnt = ffi_hw.read_reg(*reg.offset() as u64);
354    }
355
356    pub fn update_load_bsk_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
357        (1..16).for_each(|i| {
358            let reg_name = format!("runtime_3in3::pep_load_bsk_rcp_dur_pc{i}");
359            let reg = regmap
360                .register()
361                .get(&reg_name)
362                .expect("Unknown register, check regmap definition");
363            self.load_bsk_rcp_dur[i] = ffi_hw.read_reg(*reg.offset() as u64)
364        });
365    }
366    pub fn update_load_ksk_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
367        (1..16).for_each(|i| {
368            let reg_name = format!("runtime_1in3::pep_load_ksk_rcp_dur_pc{i}");
369            let reg = regmap
370                .register()
371                .get(&reg_name)
372                .expect("Unknown register, check regmap definition");
373            self.load_ksk_rcp_dur[i] = ffi_hw.read_reg(*reg.offset() as u64)
374        });
375    }
376
377    pub fn update_pep_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
378        let reg = regmap
379            .register()
380            .get("runtime_1in3::pep_ack_cnt")
381            .expect("Unknown register, check regmap definition");
382        self.pep_ack_cnt = ffi_hw.read_reg(*reg.offset() as u64);
383    }
384
385    pub fn update_pep_bskif_req_info_0(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
386        let reg = regmap
387            .register()
388            .get("runtime_3in3::pep_bskif_req_info_0")
389            .expect("Unknown register, check regmap definition");
390        let val = ffi_hw.read_reg(*reg.offset() as u64);
391        let fields = reg.as_field(val);
392        self.bskif_req_br_loop_rp = *fields.get("req_br_loop_rp").expect("Unknown field") as u16;
393        self.bskif_req_br_loop_wp = *fields.get("req_br_loop_wp").expect("Unknown field") as u16;
394    }
395
396    pub fn update_pep_bskif_req_info_1(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
397        let reg = regmap
398            .register()
399            .get("runtime_3in3::pep_bskif_req_info_1")
400            .expect("Unknown register, check regmap definition");
401        let val = ffi_hw.read_reg(*reg.offset() as u64);
402        let fields = reg.as_field(val);
403        self.bskif_req_prf_br_loop = *fields.get("req_prf_br_loop").expect("Unknown field") as u16;
404        self.bskif_req_parity = *fields.get("req_parity").expect("Unknown field") as u8;
405        self.bskif_req_assigned = *fields.get("req_assigned").expect("Unknown field") as u8;
406    }
407
408    #[allow(unused)]
409    pub fn reset(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
410        self.reset_seq_bpip_waiting_batch_cnt(ffi_hw, regmap);
411        self.reset_seq_bpip_batch_filling_cnt(ffi_hw, regmap);
412        self.reset_seq_ld_ack_cnt(ffi_hw, regmap);
413        self.reset_seq_cmux_not_full_batch_cnt(ffi_hw, regmap);
414        self.reset_seq_bpip_batch_cnt(ffi_hw, regmap);
415        self.reset_seq_bpip_batch_flush_cnt(ffi_hw, regmap);
416        self.reset_seq_bpip_batch_timeout_cnt(ffi_hw, regmap);
417        self.reset_seq_ipip_flush_cnt(ffi_hw, regmap);
418        self.reset_ldb_rcp_dur(ffi_hw, regmap);
419        self.reset_ldg_req_dur(ffi_hw, regmap);
420        self.reset_ldg_rcp_dur(ffi_hw, regmap);
421        self.reset_mmacc_sxt_rcp_dur(ffi_hw, regmap);
422        self.reset_mmacc_sxt_req_dur(ffi_hw, regmap);
423        self.reset_mmacc_sxt_cmd_wait_b_dur(ffi_hw, regmap);
424        self.reset_pep_inst_cnt(ffi_hw, regmap);
425        self.reset_pep_ack_cnt(ffi_hw, regmap);
426        self.reset_load_bsk_rcp_dur(ffi_hw, regmap);
427        self.reset_load_ksk_rcp_dur(ffi_hw, regmap);
428    }
429    #[allow(unused)]
430    pub fn reset_seq_bpip_waiting_batch_cnt(
431        &mut self,
432        ffi_hw: &mut ffi::HpuHw,
433        regmap: &FlatRegmap,
434    ) {
435        let reg = regmap
436            .register()
437            .get("runtime_1in3::pep_seq_bpip_waiting_batch_cnt")
438            .expect("Unknown register, check regmap definition");
439        ffi_hw.write_reg(*reg.offset() as u64, 0);
440    }
441    #[allow(unused)]
442    pub fn reset_seq_bpip_batch_filling_cnt(
443        &mut self,
444        ffi_hw: &mut ffi::HpuHw,
445        regmap: &FlatRegmap,
446    ) {
447        (1..16).for_each(|i| {
448            let reg_name = format!("runtime_1in3::pep_seq_bpip_batch_filling_cnt_{i}");
449            let reg = regmap
450                .register()
451                .get(&reg_name)
452                .expect("Unknown register, check regmap definition");
453            ffi_hw.write_reg(*reg.offset() as u64, 0)
454        });
455    }
456    #[allow(unused)]
457    pub fn reset_seq_ld_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
458        let reg = regmap
459            .register()
460            .get("runtime_1in3::pep_seq_ld_ack_cnt")
461            .expect("Unknown register, check regmap definition");
462        ffi_hw.write_reg(*reg.offset() as u64, 0);
463    }
464
465    #[allow(unused)]
466    pub fn reset_seq_cmux_not_full_batch_cnt(
467        &mut self,
468        ffi_hw: &mut ffi::HpuHw,
469        regmap: &FlatRegmap,
470    ) {
471        let reg = regmap
472            .register()
473            .get("runtime_1in3::pep_seq_cmux_not_full_batch_cnt")
474            .expect("Unknown register, check regmap definition");
475        ffi_hw.write_reg(*reg.offset() as u64, 0);
476    }
477
478    #[allow(unused)]
479    pub fn reset_seq_bpip_batch_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
480        let reg = regmap
481            .register()
482            .get("runtime_1in3::pep_seq_bpip_batch_cnt")
483            .expect("Unknown register, check regmap definition");
484        ffi_hw.write_reg(*reg.offset() as u64, 0);
485    }
486    #[allow(unused)]
487    pub fn reset_seq_bpip_batch_flush_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
488        let reg = regmap
489            .register()
490            .get("runtime_1in3::pep_seq_bpip_batch_flush_cnt")
491            .expect("Unknown register, check regmap definition");
492        ffi_hw.write_reg(*reg.offset() as u64, 0);
493    }
494    #[allow(unused)]
495    pub fn reset_seq_bpip_batch_timeout_cnt(
496        &mut self,
497        ffi_hw: &mut ffi::HpuHw,
498        regmap: &FlatRegmap,
499    ) {
500        let reg = regmap
501            .register()
502            .get("runtime_1in3::pep_seq_bpip_batch_timeout_cnt")
503            .expect("Unknown register, check regmap definition");
504        ffi_hw.write_reg(*reg.offset() as u64, 0);
505    }
506    #[allow(unused)]
507    pub fn reset_seq_ipip_flush_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
508        let reg = regmap
509            .register()
510            .get("runtime_1in3::pep_seq_ipip_flush_cnt")
511            .expect("Unknown register, check regmap definition");
512        ffi_hw.write_reg(*reg.offset() as u64, 0);
513    }
514    #[allow(unused)]
515    pub fn reset_ldb_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
516        let reg = regmap
517            .register()
518            .get("runtime_1in3::pep_ldb_rcp_dur")
519            .expect("Unknown register, check regmap definition");
520        ffi_hw.write_reg(*reg.offset() as u64, 0);
521    }
522    #[allow(unused)]
523    pub fn reset_ldg_req_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
524        let reg = regmap
525            .register()
526            .get("runtime_1in3::pep_ldg_req_dur")
527            .expect("Unknown register, check regmap definition");
528        ffi_hw.write_reg(*reg.offset() as u64, 0);
529    }
530    #[allow(unused)]
531    pub fn reset_ldg_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
532        let reg = regmap
533            .register()
534            .get("runtime_1in3::pep_ldg_rcp_dur")
535            .expect("Unknown register, check regmap definition");
536        ffi_hw.write_reg(*reg.offset() as u64, 0);
537    }
538    #[allow(unused)]
539    pub fn reset_mmacc_sxt_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
540        let reg = regmap
541            .register()
542            .get("runtime_1in3::pep_mmacc_sxt_rcp_dur")
543            .expect("Unknown register, check regmap definition");
544        ffi_hw.write_reg(*reg.offset() as u64, 0);
545    }
546    #[allow(unused)]
547    pub fn reset_mmacc_sxt_req_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
548        let reg = regmap
549            .register()
550            .get("runtime_1in3::pep_mmacc_sxt_req_dur")
551            .expect("Unknown register, check regmap definition");
552        ffi_hw.write_reg(*reg.offset() as u64, 0);
553    }
554    #[allow(unused)]
555    pub fn reset_mmacc_sxt_cmd_wait_b_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
556        let reg = regmap
557            .register()
558            .get("runtime_1in3::pep_mmacc_sxt_cmd_wait_b_dur")
559            .expect("Unknown register, check regmap definition");
560        ffi_hw.write_reg(*reg.offset() as u64, 0);
561    }
562
563    #[allow(unused)]
564    pub fn reset_pep_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
565        let reg = regmap
566            .register()
567            .get("runtime_1in3::pep_inst_cnt")
568            .expect("Unknown register, check regmap definition");
569        ffi_hw.write_reg(*reg.offset() as u64, 0);
570    }
571    #[allow(unused)]
572    pub fn reset_pep_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
573        let reg = regmap
574            .register()
575            .get("runtime_1in3::pep_ack_cnt")
576            .expect("Unknown register, check regmap definition");
577        ffi_hw.write_reg(*reg.offset() as u64, 0);
578    }
579
580    #[allow(unused)]
581    pub fn reset_load_bsk_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
582        (1..16).for_each(|i| {
583            let reg_name = format!("runtime_3in3::pep_load_bsk_rcp_dur_pc{i}");
584            let reg = regmap
585                .register()
586                .get(&reg_name)
587                .expect("Unknown register, check regmap definition");
588            ffi_hw.write_reg(*reg.offset() as u64, 0);
589        });
590    }
591    #[allow(unused)]
592    pub fn reset_load_ksk_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
593        (1..16).for_each(|i| {
594            let reg_name = format!("runtime_1in3::pep_load_ksk_rcp_dur_pc{i}");
595            let reg = regmap
596                .register()
597                .get(&reg_name)
598                .expect("Unknown register, check regmap definition");
599            ffi_hw.write_reg(*reg.offset() as u64, 0);
600        });
601    }
602}
603
604#[derive(Default)]
605pub struct PeMemInfo {
606    addr: u64,
607    data: [u32; 4],
608}
609impl std::fmt::Debug for PeMemInfo {
610    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
611        write!(f, "{{addr: {:x}, data: {:0>8x?}}}", self.addr, self.data)
612    }
613}
614
615#[derive(Debug, Default)]
616pub struct InfoPeMem {
617    /// PEM load input instruction counter (Could be reset by user)
618    pem_load_inst_cnt: u32,
619    /// PEM load instruction acknowledge counter (Could be reset by user)
620    pem_load_ack_cnt: u32,
621    /// PEM store input instruction counter (Could be reset by user)
622    pem_store_inst_cnt: u32,
623    /// PEM store instruction acknowledge counter (Could be reset by user)
624    pem_store_ack_cnt: u32,
625    /// PEM load first addr/data
626    pem_ld_info: [PeMemInfo; 2],
627}
628impl FromRtl for InfoPeMem {
629    fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
630        // Info structure have method to update
631        // Instead of redefine parsing here, use a default construct and update methods
632        let mut infos = Self::default();
633        infos.update(ffi_hw, regmap);
634        infos
635    }
636}
637
638/// Add facilities once created to update/reset some fields
639impl InfoPeMem {
640    pub fn update(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
641        self.update_pem_load_inst_cnt(ffi_hw, regmap);
642        self.update_pem_load_ack_cnt(ffi_hw, regmap);
643        self.update_pem_store_inst_cnt(ffi_hw, regmap);
644        self.update_pem_store_ack_cnt(ffi_hw, regmap);
645        self.update_pem_ld_info(ffi_hw, regmap, 0);
646        self.update_pem_ld_info(ffi_hw, regmap, 1);
647    }
648
649    pub fn update_pem_load_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
650        let reg = regmap
651            .register()
652            .get("runtime_1in3::pem_load_inst_cnt")
653            .expect("Unknown register, check regmap definition");
654        self.pem_load_inst_cnt = ffi_hw.read_reg(*reg.offset() as u64);
655    }
656    pub fn update_pem_load_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
657        let reg = regmap
658            .register()
659            .get("runtime_1in3::pem_load_ack_cnt")
660            .expect("Unknown register, check regmap definition");
661        self.pem_load_ack_cnt = ffi_hw.read_reg(*reg.offset() as u64);
662    }
663    pub fn update_pem_store_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
664        let reg = regmap
665            .register()
666            .get("runtime_1in3::pem_store_inst_cnt")
667            .expect("Unknown register, check regmap definition");
668        self.pem_store_inst_cnt = ffi_hw.read_reg(*reg.offset() as u64);
669    }
670    pub fn update_pem_store_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
671        let reg = regmap
672            .register()
673            .get("runtime_1in3::pem_store_ack_cnt")
674            .expect("Unknown register, check regmap definition");
675        self.pem_store_ack_cnt = ffi_hw.read_reg(*reg.offset() as u64);
676    }
677    pub fn update_pem_ld_info(
678        &mut self,
679        ffi_hw: &mut ffi::HpuHw,
680        regmap: &FlatRegmap,
681        pc_idx: usize,
682    ) {
683        // Update addr field
684        self.pem_ld_info[pc_idx].addr = ["msb", "lsb"]
685            .iter()
686            .map(|n| {
687                let reg_name = format!("runtime_1in3::pem_load_info_1_pc{pc_idx}_{n}");
688                let reg = regmap
689                    .register()
690                    .get(&reg_name)
691                    .expect("Unknown register, check regmap definition");
692                ffi_hw.read_reg(*reg.offset() as u64)
693            })
694            .fold(0_u64, |acc, v| (acc << u32::BITS) + v as u64);
695
696        // Update value field
697        (0..4).for_each(|i| {
698            let reg_name = format!("runtime_1in3::pem_load_info_0_pc{pc_idx}_{i}");
699            let reg = regmap
700                .register()
701                .get(&reg_name)
702                .expect("Unknown register, check regmap definition");
703            self.pem_ld_info[pc_idx].data[i] = ffi_hw.read_reg(*reg.offset() as u64);
704        });
705    }
706
707    #[allow(unused)]
708    pub fn reset(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
709        self.reset_pem_load_inst_cnt(ffi_hw, regmap);
710        self.reset_pem_load_ack_cnt(ffi_hw, regmap);
711        self.reset_pem_store_inst_cnt(ffi_hw, regmap);
712        self.reset_pem_store_ack_cnt(ffi_hw, regmap);
713    }
714    #[allow(unused)]
715    pub fn reset_pem_load_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
716        let reg = regmap
717            .register()
718            .get("runtime_1in3::pem_load_inst_cnt")
719            .expect("Unknown register, check regmap definition");
720        ffi_hw.write_reg(*reg.offset() as u64, 0);
721    }
722    #[allow(unused)]
723    pub fn reset_pem_load_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
724        let reg = regmap
725            .register()
726            .get("runtime_1in3::pem_load_ack_cnt")
727            .expect("Unknown register, check regmap definition");
728        ffi_hw.write_reg(*reg.offset() as u64, 0);
729    }
730    #[allow(unused)]
731    pub fn reset_pem_store_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
732        let reg = regmap
733            .register()
734            .get("runtime_1in3::pem_store_inst_cnt")
735            .expect("Unknown register, check regmap definition");
736        ffi_hw.write_reg(*reg.offset() as u64, 0);
737    }
738    #[allow(unused)]
739    pub fn reset_pem_store_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
740        let reg = regmap
741            .register()
742            .get("runtime_1in3::pem_store_ack_cnt")
743            .expect("Unknown register, check regmap definition");
744        ffi_hw.write_reg(*reg.offset() as u64, 0);
745    }
746}
747#[derive(Debug, Default)]
748pub struct InfoPeAlu {
749    /// PEA input instruction counter (Could be reset by user)
750    pea_inst_cnt: u32,
751    /// PEA instruction acknowledge counter (Could be reset by user)
752    pea_ack_cnt: u32,
753}
754impl FromRtl for InfoPeAlu {
755    fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
756        // Info structure have method to update
757        // Instead of redefine parsing here, use a default construct and update methods
758        let mut infos = Self::default();
759        infos.update(ffi_hw, regmap);
760        infos
761    }
762}
763
764/// Add facilities once created to update/reset some fields
765impl InfoPeAlu {
766    pub fn update(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
767        self.update_pea_inst_cnt(ffi_hw, regmap);
768        self.update_pea_ack_cnt(ffi_hw, regmap);
769    }
770
771    pub fn update_pea_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
772        let reg = regmap
773            .register()
774            .get("runtime_1in3::pea_inst_cnt")
775            .expect("Unknown register, check regmap definition");
776        self.pea_inst_cnt = ffi_hw.read_reg(*reg.offset() as u64);
777    }
778    pub fn update_pea_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
779        let reg = regmap
780            .register()
781            .get("runtime_1in3::pea_ack_cnt")
782            .expect("Unknown register, check regmap definition");
783        self.pea_ack_cnt = ffi_hw.read_reg(*reg.offset() as u64);
784    }
785    #[allow(unused)]
786    pub fn reset(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
787        self.reset_pea_inst_cnt(ffi_hw, regmap);
788        self.reset_pea_ack_cnt(ffi_hw, regmap);
789    }
790    #[allow(unused)]
791    pub fn reset_pea_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
792        let reg = regmap
793            .register()
794            .get("runtime_1in3::pea_inst_cnt")
795            .expect("Unknown register, check regmap definition");
796        ffi_hw.write_reg(*reg.offset() as u64, 0);
797    }
798    #[allow(unused)]
799    pub fn reset_pea_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
800        let reg = regmap
801            .register()
802            .get("runtime_1in3::pea_ack_cnt")
803            .expect("Unknown register, check regmap definition");
804        ffi_hw.write_reg(*reg.offset() as u64, 0);
805    }
806}
807
808#[derive(Default)]
809pub struct InfoIsc {
810    /// ISC input instruction counter (Could be reset by user)
811    isc_inst_cnt: u32,
812    /// ISC instruction acknowledge sample counter (Could be reset by user)
813    isc_ack_cnt: u32,
814
815    /// ISC 4 latest instructions received ([0] is the most recent)
816    isc_info: [u32; 4],
817}
818
819impl FromRtl for InfoIsc {
820    fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
821        // Info structure have method to update
822        // Instead of redefine parsing here, use a default construct and update methods
823        let mut infos = Self::default();
824        infos.update(ffi_hw, regmap);
825        infos
826    }
827}
828
829impl std::fmt::Debug for InfoIsc {
830    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
831        write!(
832            f,
833            "{{isc_inst_cnt: {}, isc_ack_cnt: {}, isc_info: {:x?}}}",
834            self.isc_inst_cnt, self.isc_ack_cnt, self.isc_info
835        )
836    }
837}
838
839/// Add facilities once created to update/reset some fields
840impl InfoIsc {
841    pub fn update(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
842        self.update_isc_inst_cnt(ffi_hw, regmap);
843        self.update_isc_ack_cnt(ffi_hw, regmap);
844        self.update_isc_info(ffi_hw, regmap);
845    }
846
847    pub fn update_isc_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
848        let reg = regmap
849            .register()
850            .get("runtime_1in3::isc_inst_cnt")
851            .expect("Unknown register, check regmap definition");
852        self.isc_inst_cnt = ffi_hw.read_reg(*reg.offset() as u64);
853    }
854    pub fn update_isc_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
855        let reg = regmap
856            .register()
857            .get("runtime_1in3::isc_ack_cnt")
858            .expect("Unknown register, check regmap definition");
859        self.isc_ack_cnt = ffi_hw.read_reg(*reg.offset() as u64);
860    }
861
862    pub fn update_isc_info(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
863        for idx in 0..4 {
864            let name = format!("runtime_1in3::isc_latest_instruction_{idx}");
865            let reg = regmap
866                .register()
867                .get(&name)
868                .expect("Unknown register, check regmap definition");
869            self.isc_info[idx] = ffi_hw.read_reg(*reg.offset() as u64);
870        }
871    }
872
873    #[allow(unused)]
874    pub fn reset(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
875        self.reset_isc_inst_cnt(ffi_hw, regmap);
876        self.reset_isc_ack_cnt(ffi_hw, regmap);
877    }
878
879    #[allow(unused)]
880    pub fn reset_isc_inst_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
881        let reg = regmap
882            .register()
883            .get("runtime_1in3::isc_inst_cnt")
884            .expect("Unknown register, check regmap definition");
885        ffi_hw.write_reg(*reg.offset() as u64, 0);
886    }
887
888    #[allow(unused)]
889    pub fn reset_isc_ack_cnt(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
890        let reg = regmap
891            .register()
892            .get("runtime_1in3::isc_ack_cnt")
893            .expect("Unknown register, check regmap definition");
894        ffi_hw.write_reg(*reg.offset() as u64, 0);
895    }
896}
897
898#[derive(Debug, Default)]
899pub struct ErrorHpu {
900    error_1in3: u32,
901    error_3in3: u32,
902}
903impl FromRtl for ErrorHpu {
904    fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
905        // Info structure have method to update
906        // Instead of redefine parsing here, use a default construct and update methods
907        let mut infos = Self::default();
908        infos.update(ffi_hw, regmap);
909        infos
910    }
911}
912
913impl ErrorHpu {
914    pub fn update(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
915        self.update_error_1in3(ffi_hw, regmap);
916        self.update_error_3in3(ffi_hw, regmap);
917    }
918
919    pub fn update_error_1in3(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
920        let reg = regmap
921            .register()
922            .get("status_1in3::error")
923            .expect("Unknown register, check regmap definition");
924        self.error_1in3 = ffi_hw.read_reg(*reg.offset() as u64);
925    }
926
927    pub fn update_error_3in3(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
928        let reg = regmap
929            .register()
930            .get("status_3in3::error")
931            .expect("Unknown register, check regmap definition");
932        self.error_3in3 = ffi_hw.read_reg(*reg.offset() as u64);
933    }
934}
tfhe_hpu_backend/interface/rtl/runtime.rs

tfhe_hpu_backend/interface/rtl/
runtime.rs
