[][src]Struct tetanes::cpu::Cpu

pub struct Cpu {
    pub cycle_count: usize,
    pub step: usize,
    pub pc: Addr,
    pub sp: Byte,
    pub acc: Byte,
    pub x: Byte,
    pub y: Byte,
    pub status: Byte,
    pub bus: Bus,
    pub pc_log: VecDeque<Addr>,
    pub stall: usize,
    pub instr: Instr,
    pub abs_addr: Addr,
    pub rel_addr: Addr,
    pub fetched_data: Byte,
    pub irq_pending: u8,
    pub nmi_pending: bool,
    // some fields omitted
}

The Central Processing Unit status and registers

Fields

cycle_count: usizestep: usizepc: Addrsp: Byteacc: Bytex: Bytey: Bytestatus: Bytebus: Buspc_log: VecDeque<Addr>stall: usizeinstr: Instrabs_addr: Addrrel_addr: Addrfetched_data: Byteirq_pending: u8nmi_pending: bool

Implementations

impl Cpu[src]

pub fn init(bus: Bus) -> Self[src]

pub fn next_instr(&self) -> Instr[src]

pub fn set_irq(&mut self, irq: Irq, val: bool)[src]

Sends an IRQ Interrupt to the CPU

http://wiki.nesdev.com/w/index.php/IRQ

pub fn has_irq(&mut self, irq: Irq) -> bool[src]

Checks if a a given IRQ is active

pub fn irq(&mut self)[src]

pub fn set_nmi(&mut self, val: bool)[src]

Sends a NMI Interrupt to the CPU

http://wiki.nesdev.com/w/index.php/NMI

pub fn peek_stackb(&self) -> Byte[src]

pub fn peek_stackw(&self) -> Addr[src]

pub fn readw(&mut self, addr: Addr) -> Addr[src]

pub fn peekw(&self, addr: Addr) -> Addr[src]

pub fn disassemble(&self, pc: &mut Addr) -> String[src]

pub fn print_instruction(&mut self, pc: Addr)[src]

Trait Implementations

impl Clocked for Cpu[src]

fn clock(&mut self) -> usize[src]

Runs the CPU one instruction

impl Clone for Cpu[src]

impl Debug for Cpu[src]

impl MemRead for Cpu[src]

impl MemWrite for Cpu[src]

impl Powered for Cpu[src]

fn power_on(&mut self)[src]

Powers on the CPU

fn reset(&mut self)[src]

Resets the CPU

Updates the PC, SP, and Status values to defined constants.

These operations take the CPU 7 cycle.

fn power_cycle(&mut self)[src]

Power cycle the CPU

Updates all status as if powered on for the first time

These operations take the CPU 7 cycle.

impl Savable for Cpu[src]

Auto Trait Implementations

impl RefUnwindSafe for Cpu

impl !Send for Cpu

impl !Sync for Cpu

impl Unpin for Cpu

impl UnwindSafe for Cpu

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> ToOwned for T where
    T: Clone
[src]

type Owned = T

The resulting type after obtaining ownership.

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<V, T> VZip<V> for T where
    V: MultiLane<T>,