ternlang_hdl/lib.rs
1// SPDX-License-Identifier: LicenseRef-Ternlang-Commercial
2// Ternlang — RFI-IRFOS Ternary Intelligence Stack
3// Copyright (C) 2026 RFI-IRFOS. All rights reserved.
4// Commercial tier. See LICENSE-COMMERCIAL in the repository root.
5// Unauthorized use, copying, or distribution is prohibited.
6
7//! ternlang-hdl — Phase 6: Hardware Description Language backend
8//!
9//! Maps ternlang/BET bytecode to synthesisable Verilog/VHDL.
10//!
11//! ## Trit → 2-bit wire pair encoding
12//!
13//! BET uses 2-bit balanced ternary encoding:
14//!
15//! 0b01 (-1) → wire pair: t1=0, t0=1 (conflict)
16//! 0b10 (+1) → wire pair: t1=1, t0=0 (truth)
17//! 0b11 ( 0) → wire pair: t1=1, t0=1 (hold)
18//! 0b00 FAULT — invalid state
19//!
20//! Each ternary variable becomes a `[1:0]` bus in Verilog.
21//!
22//! ## Modules generated
23//! - `trit_neg` — inversion
24//! - `trit_cons` — consensus (ternary OR)
25//! - `trit_mul` — ternary multiply
26//! - `trit_add` — balanced ternary adder with carry
27//! - `trit_reg` — ternary D-register (synchronous, reset to hold)
28//! - `bet_alu` — full BET ALU
29//! - Sparse matmul array (parameterised N×N)
30
31pub mod verilog;
32pub mod isa;
33pub mod sim;
34pub mod rtl_sim;
35
36pub use verilog::{VerilogEmitter, VerilogModule};
37pub use isa::BetIsaEmitter;
38pub use sim::BetSimEmitter;
39pub use rtl_sim::{BetRtlProcessor, RtlTrace, TritWire};