Crate ternlang_hdl 

ternlang-hdl — Phase 6: Hardware Description Language backend

Maps ternlang/BET bytecode to synthesisable Verilog/VHDL.

Trit → 2-bit wire pair encoding

BET uses 2-bit balanced ternary encoding:

0b01 (-1) → wire pair: t1=0, t0=1 (conflict) 0b10 (+1) → wire pair: t1=1, t0=0 (truth) 0b11 ( 0) → wire pair: t1=1, t0=1 (hold) 0b00 FAULT — invalid state

Each ternary variable becomes a [1:0] bus in Verilog.

Modules generated

• trit_neg — inversion
• trit_cons — consensus (ternary OR)
• trit_mul — ternary multiply
• trit_add — balanced ternary adder with carry
• trit_reg — ternary D-register (synchronous, reset to hold)
• bet_alu — full BET ALU
• Sparse matmul array (parameterised N×N)

Re-exports

pub use verilog::VerilogEmitter;

pub use verilog::VerilogModule;

pub use isa::BetIsaEmitter;

pub use sim::BetSimEmitter;

pub use rtl_sim::BetRtlProcessor;

pub use rtl_sim::RtlTrace;

pub use rtl_sim::TritWire;

Modules

isa

BET ISA lowering to Verilog control logic.

rtl_sim

BET Processor RTL Simulator — Phase 6.1

sim

BET FPGA Simulation Wrapper (Phase 6.1)

verilog

Verilog module generator for BET primitives.