Module lower_vector 

Vector / SIMD lowering family (wave 1, L5).

Lowers the SIMD subset of Cranelift IR that the Pliron vector dialect covers to the pure-Rust crate::lowered_ir::LoweredOp interim IR. The implementation is intentionally narrow: only the opcodes present in the cranelift-codegen version pinned by the workspace (0.111) and listed in the wave-1 spec are handled. Every other opcode returns None so the caller can fall back to its scalar/control-flow family.

Opcodes handled

The mapping below mirrors the pliron mapping table row-for-row, restricted to the entries Cranelift 0.111 actually exposes:

Cranelift opcode	Operand shape	Lowered variant
fmin	Binary (vector)	LoweredOp::VMin
fmax	Binary (vector)	LoweredOp::VMax
smin	Binary (vector)	LoweredOp::VMin
smax	Binary (vector)	LoweredOp::VMax
umin	Binary (vector)	LoweredOp::VMin
umax	Binary (vector)	LoweredOp::VMax
splat	Unary	LoweredOp::VSplat
bitselect	Ternary (vector)	LoweredOp::VSelect
vall_true	Unary	LoweredOp::VAllTrue
vany_true	Unary	LoweredOp::VAnyTrue

Opcodes deliberately not handled here

• imin_s / imin_u / imax_s / imax_u — Cranelift 0.111 names these smin/umin/smax/umax. The hyphenated aliases mentioned in the wave-1 brief don’t exist in the pinned version.
• vselect — Cranelift 0.111 has no vselect opcode. The Wasm v128.bitselect lowers to Cranelift bitselect (which can operate on either scalars or vectors); we treat the vector form as the wave-1 VSelect. The scalar form is Opcode::Bitselect with non-vector types and is routed to the conversion family by returning None.
• Scalar fmin/fmax/smin/umin/smax/umax — these are not in the vector family. We explicitly return None for the scalar case so the caller can route to crate::lower_arith / crate::lower_float.

Functions

lower_vector_inst

Lower a single vector-family Cranelift instruction to a LoweredOp.