Module t41

Teensy 4.1 specific APIs

Use from_pads to constrain the processor pads into the pins available on the Teensy 4.1. If you cannot safely acquire all processor pads, use the unsafe Pins::new method to generate pins.

Pin	Pad ID	Alt0	Alt1	Alt2	Alt3	Alt4	Alt5	Alt6	Alt7	Alt8	Alt9
34	GPIO_B1_13	WDOG1_B	LPUART5_RX	CSI_VSYNC	ENET_1588_EVENT0_OUT	FLEXIO2_FLEXIO29	GPIO2_IO29	USDHC1_WP	—	SEMC_DQS4	FLEXIO3_FLEXIO29
35	GPIO_B1_12	—	LPUART5_TX	CSI_PIXCLK	ENET_1588_EVENT0_IN	FLEXIO2_FLEXIO28	GPIO2_IO28	USDHC1_CD_B	—	—	FLEXIO3_FLEXIO28
36	GPIO_B1_02	LCD_DATA14	XBAR1_INOUT16	LPSPI4_PCS2	SAI1_TX_BCLK	FLEXIO2_FLEXIO18	GPIO2_IO18	FLEXPWM2_PWMA03	—	ENET2_RDATA01	FLEXIO3_FLEXIO18
37	GPIO_B1_03	LCD_DATA15	XBAR1_INOUT17	LPSPI4_PCS1	SAI1_TX_SYNC	FLEXIO2_FLEXIO19	GPIO2_IO19	FLEXPWM2_PWMB03	—	ENET2_RX_EN	FLEXIO3_FLEXIO19
38	GPIO_AD_B1_12	FLEXSPIA_DATA01	ACMP_OUT00	LPSPI3_PCS0	SAI1_RX_DATA00	CSI_DATA05	GPIO1_IO28	USDHC2_DATA4	KPP_ROW01	ENET2_1588_EVENT2_OUT	FLEXIO3_FLEXIO12
39	GPIO_AD_B1_13	FLEXSPIA_DATA00	ACMP_OUT01	LPSPI3_SDI	SAI1_TX_DATA00	CSI_DATA04	GPIO1_IO29	USDHC2_DATA5	KPP_COL01	ENET2_1588_EVENT2_IN	FLEXIO3_FLEXIO13
40	GPIO_AD_B1_04	FLEXSPIB_DATA03	ENET_MDC	LPUART3_CTS_B	SPDIF_SR_CLK	CSI_PIXCLK	GPIO1_IO20	USDHC2_DATA0	KPP_ROW05	GPT2_CAPTURE2	FLEXIO3_FLEXIO04
41	GPIO_AD_B1_05	FLEXSPIB_DATA02	ENET_MDIO	LPUART3_RTS_B	SPDIF_OUT	CSI_MCLK	GPIO1_IO21	USDHC2_DATA1	KPP_COL05	GPT2_COMPARE1	FLEXIO3_FLEXIO05
42	GPIO_SD_B0_03	USDHC1_DATA1	FLEXPWM1_PWMB01	LPUART8_RTS_B	XBAR1_INOUT07	LPSPI1_SDI	GPIO3_IO15	—	—	ENET2_RDATA00	SEMC_CLK6
43	GPIO_SD_B0_02	USDHC1_DATA0	FLEXPWM1_PWMA01	LPUART8_CTS_B	XBAR1_INOUT06	LPSPI1_SDO	GPIO3_IO14	—	—	ENET2_RX_ER	SEMC_CLK5
44	GPIO_SD_B0_01	USDHC1_CLK	FLEXPWM1_PWMB00	LPI2C3_SDA	XBAR1_INOUT05	LPSPI1_PCS0	GPIO3_IO13	FLEXSPIB_SS1_B	—	ENET2_TX_CLK	ENET2_REF_CLK2
45	GPIO_SD_B0_00	USDHC1_CMD	FLEXPWM1_PWMA00	LPI2C3_SCL	XBAR1_INOUT04	LPSPI1_SCK	GPIO3_IO12	FLEXSPIA_SS1_B	—	ENET2_TX_EN	SEMC_DQS4
46	GPIO_SD_B0_05	USDHC1_DATA3	FLEXPWM1_PWMB02	LPUART8_RX	XBAR1_INOUT09	FLEXSPIB_DQS	GPIO3_IO17	CCM_CLKO2	—	ENET2_RX_EN	—
47	GPIO_SD_B0_04	USDHC1_DATA2	FLEXPWM1_PWMA02	LPUART8_TX	XBAR1_INOUT08	FLEXSPIB_SS0_B	GPIO3_IO16	CCM_CLKO1	—	ENET2_RDATA01	—
48	GPIO_EMC_24	SEMC_CAS	FLEXPWM1_PWMB00	LPUART5_RX	ENET_TX_EN	GPT1_CAPTURE1	GPIO4_IO24	—	—	FLEXSPI2_A_SS0_B	—
49	GPIO_EMC_27	SEMC_CKE	FLEXPWM1_PWMA02	LPUART5_RTS_B	LPSPI1_SCK	FLEXIO1_FLEXIO13	GPIO4_IO27	—	—	FLEXSPI2_A_DATA01	—
50	GPIO_EMC_28	SEMC_WE	FLEXPWM1_PWMB02	LPUART5_CTS_B	LPSPI1_SDO	FLEXIO1_FLEXIO14	GPIO4_IO28	—	—	FLEXSPI2_A_DATA02	—
51	GPIO_EMC_22	SEMC_BA1	FLEXPWM3_PWMB03	LPI2C3_SCL	ENET_TDATA00	QTIMER2_TIMER3	GPIO4_IO22	—	—	FLEXSPI2_A_SS1_B	—
52	GPIO_EMC_26	SEMC_CLK	FLEXPWM1_PWMB01	LPUART6_RX	ENET_RX_ER	FLEXIO1_FLEXIO12	GPIO4_IO26	—	—	FLEXSPI2_A_DATA00	—
53	GPIO_EMC_25	SEMC_RAS	FLEXPWM1_PWMA01	LPUART6_TX	ENET_TX_CLK	ENET_REF_CLK	GPIO4_IO25	—	—	FLEXSPI2_A_SCLK	—
54	GPIO_EMC_29	SEMC_CS0	FLEXPWM3_PWMA00	LPUART6_RTS_B	LPSPI1_SDI	FLEXIO1_FLEXIO15	GPIO4_IO29	—	—	FLEXSPI2_A_DATA03	—

Re-exports

pub use crate::common::*;

Structs

Pins

Teensy 4.1 pins

Functions

from_pads

Constrain the processor pads to the Teensy 4.1 pins

Type Aliases

ErasedPins

Type-erased Teensy 4.1 pins

P34

Pin 34 (4.1)

P35

Pin 35 (4.1)

P36

Pin 36 (4.1)

P37

Pin 37 (4.1)

P38

Pin 38 (4.1)

P39

Pin 39 (4.1)

P40

Pin 40 (4.1)

P41

Pin 41 (4.1)

P42

Pin 42 (4.1)

P43

Pin 43 (4.1)

P44

Pin 44 (4.1)

P45

Pin 45 (4.1)

P46

Pin 46 (4.1)

P47

Pin 47 (4.1)

P48

Pin 48 (4.1)

P49

Pin 49 (4.1)

P50

Pin 50 (4.1)

P51

Pin 51 (4.1)

P52

Pin 52 (4.1)

P53

Pin 53 (4.1)

P54

Pin 54 (4.1)