teensy4_pins/t41.rs
1//! Teensy 4.1 specific APIs
2//!
3//! Use [`from_pads`](from_pads()) to constrain the processor pads into the pins available on the Teensy 4.1.
4//! If you cannot safely acquire all processor pads, use the unsafe [`Pins::new`](Pins::new())
5//! method to generate pins.
6//!
7//! | Pin | Pad ID | Alt0 | Alt1 | Alt2 | Alt3 | Alt4 | Alt5 | Alt6 | Alt7 | Alt8 | Alt9 |
8//! | ---- | ------------- | --------------- | --------------- | ------------- | -------------------- | ---------------- | ---------- | --------------- | --------- | --------------------- | ---------------- |
9//! | 34 | GPIO_B1_13 | WDOG1_B | LPUART5_RX | CSI_VSYNC | ENET_1588_EVENT0_OUT | FLEXIO2_FLEXIO29 | GPIO2_IO29 | USDHC1_WP | --- | SEMC_DQS4 | FLEXIO3_FLEXIO29 |
10//! | 35 | GPIO_B1_12 | --- | LPUART5_TX | CSI_PIXCLK | ENET_1588_EVENT0_IN | FLEXIO2_FLEXIO28 | GPIO2_IO28 | USDHC1_CD_B | --- | --- | FLEXIO3_FLEXIO28 |
11//! | 36 | GPIO_B1_02 | LCD_DATA14 | XBAR1_INOUT16 | LPSPI4_PCS2 | SAI1_TX_BCLK | FLEXIO2_FLEXIO18 | GPIO2_IO18 | FLEXPWM2_PWMA03 | --- | ENET2_RDATA01 | FLEXIO3_FLEXIO18 |
12//! | 37 | GPIO_B1_03 | LCD_DATA15 | XBAR1_INOUT17 | LPSPI4_PCS1 | SAI1_TX_SYNC | FLEXIO2_FLEXIO19 | GPIO2_IO19 | FLEXPWM2_PWMB03 | --- | ENET2_RX_EN | FLEXIO3_FLEXIO19 |
13//! | 38 | GPIO_AD_B1_12 | FLEXSPIA_DATA01 | ACMP_OUT00 | LPSPI3_PCS0 | SAI1_RX_DATA00 | CSI_DATA05 | GPIO1_IO28 | USDHC2_DATA4 | KPP_ROW01 | ENET2_1588_EVENT2_OUT | FLEXIO3_FLEXIO12 |
14//! | 39 | GPIO_AD_B1_13 | FLEXSPIA_DATA00 | ACMP_OUT01 | LPSPI3_SDI | SAI1_TX_DATA00 | CSI_DATA04 | GPIO1_IO29 | USDHC2_DATA5 | KPP_COL01 | ENET2_1588_EVENT2_IN | FLEXIO3_FLEXIO13 |
15//! | 40 | GPIO_AD_B1_04 | FLEXSPIB_DATA03 | ENET_MDC | LPUART3_CTS_B | SPDIF_SR_CLK | CSI_PIXCLK | GPIO1_IO20 | USDHC2_DATA0 | KPP_ROW05 | GPT2_CAPTURE2 | FLEXIO3_FLEXIO04 |
16//! | 41 | GPIO_AD_B1_05 | FLEXSPIB_DATA02 | ENET_MDIO | LPUART3_RTS_B | SPDIF_OUT | CSI_MCLK | GPIO1_IO21 | USDHC2_DATA1 | KPP_COL05 | GPT2_COMPARE1 | FLEXIO3_FLEXIO05 |
17//! | 42 | GPIO_SD_B0_03 | USDHC1_DATA1 | FLEXPWM1_PWMB01 | LPUART8_RTS_B | XBAR1_INOUT07 | LPSPI1_SDI | GPIO3_IO15 | --- | --- | ENET2_RDATA00 | SEMC_CLK6 |
18//! | 43 | GPIO_SD_B0_02 | USDHC1_DATA0 | FLEXPWM1_PWMA01 | LPUART8_CTS_B | XBAR1_INOUT06 | LPSPI1_SDO | GPIO3_IO14 | --- | --- | ENET2_RX_ER | SEMC_CLK5 |
19//! | 44 | GPIO_SD_B0_01 | USDHC1_CLK | FLEXPWM1_PWMB00 | LPI2C3_SDA | XBAR1_INOUT05 | LPSPI1_PCS0 | GPIO3_IO13 | FLEXSPIB_SS1_B | --- | ENET2_TX_CLK | ENET2_REF_CLK2 |
20//! | 45 | GPIO_SD_B0_00 | USDHC1_CMD | FLEXPWM1_PWMA00 | LPI2C3_SCL | XBAR1_INOUT04 | LPSPI1_SCK | GPIO3_IO12 | FLEXSPIA_SS1_B | --- | ENET2_TX_EN | SEMC_DQS4 |
21//! | 46 | GPIO_SD_B0_05 | USDHC1_DATA3 | FLEXPWM1_PWMB02 | LPUART8_RX | XBAR1_INOUT09 | FLEXSPIB_DQS | GPIO3_IO17 | CCM_CLKO2 | --- | ENET2_RX_EN | --- |
22//! | 47 | GPIO_SD_B0_04 | USDHC1_DATA2 | FLEXPWM1_PWMA02 | LPUART8_TX | XBAR1_INOUT08 | FLEXSPIB_SS0_B | GPIO3_IO16 | CCM_CLKO1 | --- | ENET2_RDATA01 | --- |
23//! | 48 | GPIO_EMC_24 | SEMC_CAS | FLEXPWM1_PWMB00 | LPUART5_RX | ENET_TX_EN | GPT1_CAPTURE1 | GPIO4_IO24 | --- | --- | FLEXSPI2_A_SS0_B | --- |
24//! | 49 | GPIO_EMC_27 | SEMC_CKE | FLEXPWM1_PWMA02 | LPUART5_RTS_B | LPSPI1_SCK | FLEXIO1_FLEXIO13 | GPIO4_IO27 | --- | --- | FLEXSPI2_A_DATA01 | --- |
25//! | 50 | GPIO_EMC_28 | SEMC_WE | FLEXPWM1_PWMB02 | LPUART5_CTS_B | LPSPI1_SDO | FLEXIO1_FLEXIO14 | GPIO4_IO28 | --- | --- | FLEXSPI2_A_DATA02 | --- |
26//! | 51 | GPIO_EMC_22 | SEMC_BA1 | FLEXPWM3_PWMB03 | LPI2C3_SCL | ENET_TDATA00 | QTIMER2_TIMER3 | GPIO4_IO22 | --- | --- | FLEXSPI2_A_SS1_B | --- |
27//! | 52 | GPIO_EMC_26 | SEMC_CLK | FLEXPWM1_PWMB01 | LPUART6_RX | ENET_RX_ER | FLEXIO1_FLEXIO12 | GPIO4_IO26 | --- | --- | FLEXSPI2_A_DATA00 | --- |
28//! | 53 | GPIO_EMC_25 | SEMC_RAS | FLEXPWM1_PWMA01 | LPUART6_TX | ENET_TX_CLK | ENET_REF_CLK | GPIO4_IO25 | --- | --- | FLEXSPI2_A_SCLK | --- |
29//! | 54 | GPIO_EMC_29 | SEMC_CS0 | FLEXPWM3_PWMA00 | LPUART6_RTS_B | LPSPI1_SDI | FLEXIO1_FLEXIO15 | GPIO4_IO29 | --- | --- | FLEXSPI2_A_DATA03 | --- |
30
31pub use crate::common::*;
32use crate::iomuxc::{gpio_ad_b1::*, gpio_b1::*, gpio_emc::*, gpio_sd_b0::*, ErasedPad};
33
34/// Pin 34 (4.1)
35pub type P34 = GPIO_B1_13;
36/// Pin 35 (4.1)
37pub type P35 = GPIO_B1_12;
38/// Pin 36 (4.1)
39pub type P36 = GPIO_B1_02;
40/// Pin 37 (4.1)
41pub type P37 = GPIO_B1_03;
42/// Pin 38 (4.1)
43pub type P38 = GPIO_AD_B1_12;
44/// Pin 39 (4.1)
45pub type P39 = GPIO_AD_B1_13;
46/// Pin 40 (4.1)
47pub type P40 = GPIO_AD_B1_04;
48/// Pin 41 (4.1)
49pub type P41 = GPIO_AD_B1_05;
50/// Pin 42 (4.1)
51pub type P42 = GPIO_SD_B0_03;
52/// Pin 43 (4.1)
53pub type P43 = GPIO_SD_B0_02;
54/// Pin 44 (4.1)
55pub type P44 = GPIO_SD_B0_01;
56/// Pin 45 (4.1)
57pub type P45 = GPIO_SD_B0_00;
58/// Pin 46 (4.1)
59pub type P46 = GPIO_SD_B0_05;
60/// Pin 47 (4.1)
61pub type P47 = GPIO_SD_B0_04;
62/// Pin 48 (4.1)
63pub type P48 = GPIO_EMC_24;
64/// Pin 49 (4.1)
65pub type P49 = GPIO_EMC_27;
66/// Pin 50 (4.1)
67pub type P50 = GPIO_EMC_28;
68/// Pin 51 (4.1)
69pub type P51 = GPIO_EMC_22;
70/// Pin 52 (4.1)
71pub type P52 = GPIO_EMC_26;
72/// Pin 53 (4.1)
73pub type P53 = GPIO_EMC_25;
74/// Pin 54 (4.1)
75pub type P54 = GPIO_EMC_29;
76
77/// Type-erased Teensy 4.1 pins
78///
79/// To get pin 13, the LED, index into the 13th element of this array:
80/// `erased_pins[13]`.
81///
82/// Use [`Pins::erase`](Pins::erase()) to erase pin types.
83pub type ErasedPins = [ErasedPad; 55];
84
85/// Teensy 4.1 pins
86///
87/// See [`from_pads`](from_pads()) to safely constrain the processor's pads, and acquire
88/// Teensy 4.1 pins. Or, use [`new`](Pins::new()) to unsafely create pins.
89pub struct Pins {
90 /// Pin 0
91 pub p0: P0,
92 /// Pin 1
93 pub p1: P1,
94 /// Pin 2
95 pub p2: P2,
96 /// Pin 3
97 pub p3: P3,
98 /// Pin 4
99 pub p4: P4,
100 /// Pin 5
101 pub p5: P5,
102 /// Pin 6
103 pub p6: P6,
104 /// Pin 7
105 pub p7: P7,
106 /// Pin 8
107 pub p8: P8,
108 /// Pin 9
109 pub p9: P9,
110 /// Pin 10
111 pub p10: P10,
112 /// Pin 11
113 pub p11: P11,
114 /// Pin 12
115 pub p12: P12,
116 /// Pin 13
117 pub p13: P13,
118 /// Pin 14
119 pub p14: P14,
120 /// Pin 15
121 pub p15: P15,
122 /// Pin 16
123 pub p16: P16,
124 /// Pin 17
125 pub p17: P17,
126 /// Pin 18
127 pub p18: P18,
128 /// Pin 19
129 pub p19: P19,
130 /// Pin 20
131 pub p20: P20,
132 /// Pin 21
133 pub p21: P21,
134 /// Pin 22
135 pub p22: P22,
136 /// Pin 23
137 pub p23: P23,
138 /// Pin 24
139 pub p24: P24,
140 /// Pin 25
141 pub p25: P25,
142 /// Pin 26
143 pub p26: P26,
144 /// Pin 27
145 pub p27: P27,
146 /// Pin 28
147 pub p28: P28,
148 /// Pin 29
149 pub p29: P29,
150 /// Pin 30
151 pub p30: P30,
152 /// Pin 31
153 pub p31: P31,
154 /// Pin 32
155 pub p32: P32,
156 /// Pin 33
157 pub p33: P33,
158 // END OF COMMON PINS
159 /// Pin 34
160 pub p34: P34,
161 /// Pin 35
162 pub p35: P35,
163 /// Pin 36
164 pub p36: P36,
165 /// Pin 37
166 pub p37: P37,
167 /// Pin 38
168 pub p38: P38,
169 /// Pin 39
170 pub p39: P39,
171 /// Pin 40
172 pub p40: P40,
173 /// Pin 41
174 pub p41: P41,
175 /// Pin 42
176 pub p42: P42,
177 /// Pin 43
178 pub p43: P43,
179 /// Pin 44
180 pub p44: P44,
181 /// Pin 45
182 pub p45: P45,
183 /// Pin 46
184 pub p46: P46,
185 /// Pin 47
186 pub p47: P47,
187 /// Pin 48
188 pub p48: P48,
189 /// Pin 49
190 pub p49: P49,
191 /// Pin 50
192 pub p50: P50,
193 /// Pin 51
194 pub p51: P51,
195 /// Pin 52
196 pub p52: P52,
197 /// Pin 53
198 pub p53: P53,
199 /// Pin 54
200 pub p54: P54,
201}
202
203/// Constrain the processor pads to the Teensy 4.1 pins
204#[inline]
205pub const fn from_pads(iomuxc: crate::iomuxc::Pads) -> Pins {
206 Pins {
207 p0: iomuxc.gpio_ad_b0.p03,
208 p1: iomuxc.gpio_ad_b0.p02,
209 p2: iomuxc.gpio_emc.p04,
210 p3: iomuxc.gpio_emc.p05,
211 p4: iomuxc.gpio_emc.p06,
212 p5: iomuxc.gpio_emc.p08,
213 p6: iomuxc.gpio_b0.p10,
214 p7: iomuxc.gpio_b1.p01,
215 p8: iomuxc.gpio_b1.p00,
216 p9: iomuxc.gpio_b0.p11,
217 p10: iomuxc.gpio_b0.p00,
218 p11: iomuxc.gpio_b0.p02,
219 p12: iomuxc.gpio_b0.p01,
220 p13: iomuxc.gpio_b0.p03,
221 p14: iomuxc.gpio_ad_b1.p02,
222 p15: iomuxc.gpio_ad_b1.p03,
223 p16: iomuxc.gpio_ad_b1.p07,
224 p17: iomuxc.gpio_ad_b1.p06,
225 p18: iomuxc.gpio_ad_b1.p01,
226 p19: iomuxc.gpio_ad_b1.p00,
227 p20: iomuxc.gpio_ad_b1.p10,
228 p21: iomuxc.gpio_ad_b1.p11,
229 p22: iomuxc.gpio_ad_b1.p08,
230 p23: iomuxc.gpio_ad_b1.p09,
231 p24: iomuxc.gpio_ad_b0.p12,
232 p25: iomuxc.gpio_ad_b0.p13,
233 p26: iomuxc.gpio_ad_b1.p14,
234 p27: iomuxc.gpio_ad_b1.p15,
235 p28: iomuxc.gpio_emc.p32,
236 p29: iomuxc.gpio_emc.p31,
237 p30: iomuxc.gpio_emc.p37,
238 p31: iomuxc.gpio_emc.p36,
239 p32: iomuxc.gpio_b0.p12,
240 p33: iomuxc.gpio_emc.p07,
241 // END OF COMMON PINS
242 p34: iomuxc.gpio_b1.p13,
243 p35: iomuxc.gpio_b1.p12,
244 p36: iomuxc.gpio_b1.p02,
245 p37: iomuxc.gpio_b1.p03,
246 p38: iomuxc.gpio_ad_b1.p12,
247 p39: iomuxc.gpio_ad_b1.p13,
248 p40: iomuxc.gpio_ad_b1.p04,
249 p41: iomuxc.gpio_ad_b1.p05,
250 p42: iomuxc.gpio_sd_b0.p03,
251 p43: iomuxc.gpio_sd_b0.p02,
252 p44: iomuxc.gpio_sd_b0.p01,
253 p45: iomuxc.gpio_sd_b0.p00,
254 p46: iomuxc.gpio_sd_b0.p05,
255 p47: iomuxc.gpio_sd_b0.p04,
256 p48: iomuxc.gpio_emc.p24,
257 p49: iomuxc.gpio_emc.p27,
258 p50: iomuxc.gpio_emc.p28,
259 p51: iomuxc.gpio_emc.p22,
260 p52: iomuxc.gpio_emc.p26,
261 p53: iomuxc.gpio_emc.p25,
262 p54: iomuxc.gpio_emc.p29,
263 }
264}
265
266impl Pins {
267 /// Create an instance of `Pins` when you do not have a handle
268 /// to the processor pads
269 ///
270 /// # Safety
271 ///
272 /// Caller must ensure that the pins are not aliased elsewhere in
273 /// the program. This could include
274 ///
275 /// - an existing handle to the `imxrt-iomuxc` pads,
276 /// - another instance of `Pins` that was safely acquired
277 /// using [`from_pads`](from_pads()).
278 #[inline]
279 pub const unsafe fn new() -> Self {
280 from_pads(crate::iomuxc::Pads::new())
281 }
282
283 /// Erase the types of all pins
284 #[inline]
285 pub fn erase(self) -> ErasedPins {
286 [
287 self.p0.erase(),
288 self.p1.erase(),
289 self.p2.erase(),
290 self.p3.erase(),
291 self.p4.erase(),
292 self.p5.erase(),
293 self.p6.erase(),
294 self.p7.erase(),
295 self.p8.erase(),
296 self.p9.erase(),
297 self.p10.erase(),
298 self.p11.erase(),
299 self.p12.erase(),
300 self.p13.erase(),
301 self.p14.erase(),
302 self.p15.erase(),
303 self.p16.erase(),
304 self.p17.erase(),
305 self.p18.erase(),
306 self.p19.erase(),
307 self.p20.erase(),
308 self.p21.erase(),
309 self.p22.erase(),
310 self.p23.erase(),
311 self.p24.erase(),
312 self.p25.erase(),
313 self.p26.erase(),
314 self.p27.erase(),
315 self.p28.erase(),
316 self.p29.erase(),
317 self.p30.erase(),
318 self.p31.erase(),
319 self.p32.erase(),
320 self.p33.erase(),
321 // END OF COMMON PINS
322 self.p34.erase(),
323 self.p35.erase(),
324 self.p36.erase(),
325 self.p37.erase(),
326 self.p38.erase(),
327 self.p39.erase(),
328 self.p40.erase(),
329 self.p41.erase(),
330 self.p42.erase(),
331 self.p43.erase(),
332 self.p44.erase(),
333 self.p45.erase(),
334 self.p46.erase(),
335 self.p47.erase(),
336 self.p48.erase(),
337 self.p49.erase(),
338 self.p50.erase(),
339 self.p51.erase(),
340 self.p52.erase(),
341 self.p53.erase(),
342 self.p54.erase(),
343 ]
344 }
345}