Module target_features::docs::riscv
source · Expand description
riscv documentation
Features
| Feature | Description | Also Enables† |
|---|---|---|
a | ‘A’ (Atomic Instructions). | |
c | ‘C’ (Compressed Instructions). | |
d | ‘D’ (Double-Precision Floating-Point). | f |
e | Implements RV{32,64}E (provides 16 rather than 32 GPRs). | |
f | ‘F’ (Single-Precision Floating-Point). | |
m | ‘M’ (Integer Multiplication and Division). | |
relax | Enable Linker relaxation.. | |
unaligned-scalar-mem | Has reasonably performant unaligned scalar loads and stores. | |
v | ‘V’ (Vector Extension for Application Processors). | d, f |
zba | ‘Zba’ (Address Generation Instructions). | |
zbb | ‘Zbb’ (Basic Bit-Manipulation). | |
zbc | ‘Zbc’ (Carry-Less Multiplication). | |
zbkb | ‘Zbkb’ (Bitmanip instructions for Cryptography). | |
zbkc | ‘Zbkc’ (Carry-less multiply instructions for Cryptography). | |
zbkx | ‘Zbkx’ (Crossbar permutation instructions). | |
zbs | ‘Zbs’ (Single-Bit Instructions). | |
zdinx | ‘Zdinx’ (Double in Integer). | zfinx |
zfh | ‘Zfh’ (Half-Precision Floating-Point). | f |
zfhmin | ‘Zfhmin’ (Half-Precision Floating-Point Minimal). | f |
zfinx | ‘Zfinx’ (Float in Integer). | |
zhinx | ‘Zhinx’ (Half Float in Integer). | zfinx |
zhinxmin | ‘Zhinxmin’ (Half Float in Integer Minimal). | zfinx |
zk | ‘Zk’ (Standard scalar cryptography extension). | zbkb, zbkc, zbkx, zkn, zknd, zkne, zknh, zkr, zkt |
zkn | ‘Zkn’ (NIST Algorithm Suite). | zbkb, zbkc, zbkx, zknd, zkne, zknh |
zknd | ‘Zknd’ (NIST Suite: AES Decryption). | |
zkne | ‘Zkne’ (NIST Suite: AES Encryption). | |
zknh | ‘Zknh’ (NIST Suite: Hash Function Instructions). | |
zkr | ‘Zkr’ (Entropy Source Extension). | |
zks | ‘Zks’ (ShangMi Algorithm Suite). | zbkb, zbkc, zbkx, zksed, zksh |
zksed | ‘Zksed’ (ShangMi Suite: SM4 Block Cipher Instructions). | |
zksh | ‘Zksh’ (ShangMi Suite: SM3 Hash Function Instructions). | |
zkt | ‘Zkt’ (Data Independent Execution Latency). | |
crt-static | Enables C Run-time Libraries to be statically linked. |
† This is often empirical, rather than specified in any standard, i.e. all available CPUs with a particular feature also have another feature.
CPUs
| CPU | Enabled Features |
|---|---|
generic | a, c, d, f, m |
generic-rv32 | a, c, d, f, m |
generic-rv64 | a, c, d, f, m |
rocket | a, c, d, f, m |
rocket-rv32 | a, c, d, f, m |
rocket-rv64 | a, c, d, f, m |
sifive-7-series | a, c, d, f, m |
sifive-e20 | a, c, d, f, m |
sifive-e21 | a, c, d, f, m |
sifive-e24 | a, c, d, f, m |
sifive-e31 | a, c, d, f, m |
sifive-e34 | a, c, d, f, m |
sifive-e76 | a, c, d, f, m |
sifive-s21 | a, c, d, f, m |
sifive-s51 | a, c, d, f, m |
sifive-s54 | a, c, d, f, m |
sifive-s76 | a, c, d, f, m |
sifive-u54 | a, c, d, f, m |
sifive-u74 | a, c, d, f, m |
sifive-x280 | a, c, d, f, m, v, zba, zbb, zfh, zfhmin |
syntacore-scr1-base | a, c, d, f, m |
syntacore-scr1-max | a, c, d, f, m |