Crate synth_backend_riscv 

RISC-V backend for synth — RV32IMAC encoder, ELF builder, PMP allocator.

Mirrors the structure of synth-backend (ARM Cortex-M) but emits RISC-V machine code. The instruction selector lives in synth-synthesis::riscv; this crate contains the binary encoder, ELF emission, linker script generation, and Physical Memory Protection (PMP) allocator.

Supported variants (per TargetSpec::IsaVariant::RiscV32 { extensions }):

• RV32I — base 32-bit integer
• RV32IM — adds multiply/divide
• RV32IMA — adds atomics
• RV32IMAC — adds compressed (16-bit) instructions

The encoder always emits 32-bit instructions in this skeleton. The 16-bit C-extension encoding will be a peephole pass in a follow-up.

Re-exports

pub use backend::RiscVBackend;

pub use elf_builder::ElfMode;

pub use elf_builder::RiscVElfBuilder;

pub use elf_builder::RiscVElfFunction;

pub use encoder::RiscVEncoder;

pub use encoder::RiscVEncodingError;

pub use linker_script::LinkerScriptConfig;

pub use linker_script::RiscVLinkerScriptGenerator;

pub use pmp::PMPAllocator;

pub use pmp::PMPEntry;

pub use pmp::PMPError;

pub use pmp::PMPMode;

pub use pmp::PMPPermissions;

pub use register::Reg;

pub use register::RegClass;

pub use riscv_op::Branch;

pub use riscv_op::Csr;

pub use riscv_op::RiscVOp;

pub use selector::RiscVSelection;

pub use selector::RvBoundsMode;

pub use selector::SelectorError;

pub use selector::SelectorOptions;

pub use selector::select_simple;

pub use selector::select_with_options;

pub use selector::select_with_result_types;

pub use startup::RiscVStartupGenerator;

pub use startup::StartupConfig;

Modules

backend

RISC-V Backend trait implementation — plumbs the selector + encoder + ELF builder behind the same interface as synth_backend::ArmBackend.

elf_builder

Minimal RISC-V ELF builder — emits ET_REL or ET_EXEC for RV32IMAC.

encoder

RV32 instruction encoder — translates RiscVOp to 32-bit machine words.

linker_script

GNU ld linker script generator for RISC-V targets.

pmp

Physical Memory Protection (PMP) allocator.

register

RISC-V register file (RV32 / RV64 share the same 32 GPR namespace).

riscv_op

RISC-V instruction representation.

selector

WASM → RV32 instruction selector.

startup

RISC-V bare-metal startup code generator.