synopsys_usb_otg/ral/peripherals/otg_fs_device_v1.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! USB on the go full speed
4//!
5//! Used by: stm32f401, stm32f405, stm32f407, stm32f411, stm32f427, stm32f429
6
7use super::super::register::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// OTG_FS device configuration register (OTG_FS_DCFG)
12pub mod DCFG {
13
14 /// Device speed
15 pub mod DSPD {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (2 bits: 0b11 << 0)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Non-zero-length status OUT handshake
29 pub mod NZLSOHSK {
30 /// Offset (2 bits)
31 pub const offset: u32 = 2;
32 /// Mask (1 bit: 1 << 2)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Device address
43 pub mod DAD {
44 /// Offset (4 bits)
45 pub const offset: u32 = 4;
46 /// Mask (7 bits: 0x7f << 4)
47 pub const mask: u32 = 0x7f << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Periodic frame interval
57 pub mod PFIVL {
58 /// Offset (11 bits)
59 pub const offset: u32 = 11;
60 /// Mask (2 bits: 0b11 << 11)
61 pub const mask: u32 = 0b11 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69}
70
71/// OTG_FS device control register (OTG_FS_DCTL)
72pub mod DCTL {
73
74 /// Remote wakeup signaling
75 pub mod RWUSIG {
76 /// Offset (0 bits)
77 pub const offset: u32 = 0;
78 /// Mask (1 bit: 1 << 0)
79 pub const mask: u32 = 1 << offset;
80 /// Read-only values (empty)
81 pub mod R {}
82 /// Write-only values (empty)
83 pub mod W {}
84 /// Read-write values (empty)
85 pub mod RW {}
86 }
87
88 /// Soft disconnect
89 pub mod SDIS {
90 /// Offset (1 bits)
91 pub const offset: u32 = 1;
92 /// Mask (1 bit: 1 << 1)
93 pub const mask: u32 = 1 << offset;
94 /// Read-only values (empty)
95 pub mod R {}
96 /// Write-only values (empty)
97 pub mod W {}
98 /// Read-write values (empty)
99 pub mod RW {}
100 }
101
102 /// Global IN NAK status
103 pub mod GINSTS {
104 /// Offset (2 bits)
105 pub const offset: u32 = 2;
106 /// Mask (1 bit: 1 << 2)
107 pub const mask: u32 = 1 << offset;
108 /// Read-only values (empty)
109 pub mod R {}
110 /// Write-only values (empty)
111 pub mod W {}
112 /// Read-write values (empty)
113 pub mod RW {}
114 }
115
116 /// Global OUT NAK status
117 pub mod GONSTS {
118 /// Offset (3 bits)
119 pub const offset: u32 = 3;
120 /// Mask (1 bit: 1 << 3)
121 pub const mask: u32 = 1 << offset;
122 /// Read-only values (empty)
123 pub mod R {}
124 /// Write-only values (empty)
125 pub mod W {}
126 /// Read-write values (empty)
127 pub mod RW {}
128 }
129
130 /// Test control
131 pub mod TCTL {
132 /// Offset (4 bits)
133 pub const offset: u32 = 4;
134 /// Mask (3 bits: 0b111 << 4)
135 pub const mask: u32 = 0b111 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// Set global IN NAK
145 pub mod SGINAK {
146 /// Offset (7 bits)
147 pub const offset: u32 = 7;
148 /// Mask (1 bit: 1 << 7)
149 pub const mask: u32 = 1 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157
158 /// Clear global IN NAK
159 pub mod CGINAK {
160 /// Offset (8 bits)
161 pub const offset: u32 = 8;
162 /// Mask (1 bit: 1 << 8)
163 pub const mask: u32 = 1 << offset;
164 /// Read-only values (empty)
165 pub mod R {}
166 /// Write-only values (empty)
167 pub mod W {}
168 /// Read-write values (empty)
169 pub mod RW {}
170 }
171
172 /// Set global OUT NAK
173 pub mod SGONAK {
174 /// Offset (9 bits)
175 pub const offset: u32 = 9;
176 /// Mask (1 bit: 1 << 9)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// Clear global OUT NAK
187 pub mod CGONAK {
188 /// Offset (10 bits)
189 pub const offset: u32 = 10;
190 /// Mask (1 bit: 1 << 10)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// Power-on programming done
201 pub mod POPRGDNE {
202 /// Offset (11 bits)
203 pub const offset: u32 = 11;
204 /// Mask (1 bit: 1 << 11)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213}
214
215/// OTG_FS device status register (OTG_FS_DSTS)
216pub mod DSTS {
217
218 /// Suspend status
219 pub mod SUSPSTS {
220 /// Offset (0 bits)
221 pub const offset: u32 = 0;
222 /// Mask (1 bit: 1 << 0)
223 pub const mask: u32 = 1 << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231
232 /// Enumerated speed
233 pub mod ENUMSPD {
234 /// Offset (1 bits)
235 pub const offset: u32 = 1;
236 /// Mask (2 bits: 0b11 << 1)
237 pub const mask: u32 = 0b11 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values (empty)
243 pub mod RW {}
244 }
245
246 /// Erratic error
247 pub mod EERR {
248 /// Offset (3 bits)
249 pub const offset: u32 = 3;
250 /// Mask (1 bit: 1 << 3)
251 pub const mask: u32 = 1 << offset;
252 /// Read-only values (empty)
253 pub mod R {}
254 /// Write-only values (empty)
255 pub mod W {}
256 /// Read-write values (empty)
257 pub mod RW {}
258 }
259
260 /// Frame number of the received SOF
261 pub mod FNSOF {
262 /// Offset (8 bits)
263 pub const offset: u32 = 8;
264 /// Mask (14 bits: 0x3fff << 8)
265 pub const mask: u32 = 0x3fff << offset;
266 /// Read-only values (empty)
267 pub mod R {}
268 /// Write-only values (empty)
269 pub mod W {}
270 /// Read-write values (empty)
271 pub mod RW {}
272 }
273}
274
275/// OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
276pub mod DIEPMSK {
277
278 /// Transfer completed interrupt mask
279 pub mod XFRCM {
280 /// Offset (0 bits)
281 pub const offset: u32 = 0;
282 /// Mask (1 bit: 1 << 0)
283 pub const mask: u32 = 1 << offset;
284 /// Read-only values (empty)
285 pub mod R {}
286 /// Write-only values (empty)
287 pub mod W {}
288 /// Read-write values (empty)
289 pub mod RW {}
290 }
291
292 /// Endpoint disabled interrupt mask
293 pub mod EPDM {
294 /// Offset (1 bits)
295 pub const offset: u32 = 1;
296 /// Mask (1 bit: 1 << 1)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// Timeout condition mask (Non-isochronous endpoints)
307 pub mod TOM {
308 /// Offset (3 bits)
309 pub const offset: u32 = 3;
310 /// Mask (1 bit: 1 << 3)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319
320 /// IN token received when TxFIFO empty mask
321 pub mod ITTXFEMSK {
322 /// Offset (4 bits)
323 pub const offset: u32 = 4;
324 /// Mask (1 bit: 1 << 4)
325 pub const mask: u32 = 1 << offset;
326 /// Read-only values (empty)
327 pub mod R {}
328 /// Write-only values (empty)
329 pub mod W {}
330 /// Read-write values (empty)
331 pub mod RW {}
332 }
333
334 /// IN token received with EP mismatch mask
335 pub mod INEPNMM {
336 /// Offset (5 bits)
337 pub const offset: u32 = 5;
338 /// Mask (1 bit: 1 << 5)
339 pub const mask: u32 = 1 << offset;
340 /// Read-only values (empty)
341 pub mod R {}
342 /// Write-only values (empty)
343 pub mod W {}
344 /// Read-write values (empty)
345 pub mod RW {}
346 }
347
348 /// IN endpoint NAK effective mask
349 pub mod INEPNEM {
350 /// Offset (6 bits)
351 pub const offset: u32 = 6;
352 /// Mask (1 bit: 1 << 6)
353 pub const mask: u32 = 1 << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values (empty)
359 pub mod RW {}
360 }
361}
362
363/// OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
364pub mod DOEPMSK {
365
366 /// Transfer completed interrupt mask
367 pub mod XFRCM {
368 /// Offset (0 bits)
369 pub const offset: u32 = 0;
370 /// Mask (1 bit: 1 << 0)
371 pub const mask: u32 = 1 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379
380 /// Endpoint disabled interrupt mask
381 pub mod EPDM {
382 /// Offset (1 bits)
383 pub const offset: u32 = 1;
384 /// Mask (1 bit: 1 << 1)
385 pub const mask: u32 = 1 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// SETUP phase done mask
395 pub mod STUPM {
396 /// Offset (3 bits)
397 pub const offset: u32 = 3;
398 /// Mask (1 bit: 1 << 3)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// OUT token received when endpoint disabled mask
409 pub mod OTEPDM {
410 /// Offset (4 bits)
411 pub const offset: u32 = 4;
412 /// Mask (1 bit: 1 << 4)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421}
422
423/// OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
424pub mod DAINT {
425
426 /// IN endpoint interrupt bits
427 pub mod IEPINT {
428 /// Offset (0 bits)
429 pub const offset: u32 = 0;
430 /// Mask (16 bits: 0xffff << 0)
431 pub const mask: u32 = 0xffff << offset;
432 /// Read-only values (empty)
433 pub mod R {}
434 /// Write-only values (empty)
435 pub mod W {}
436 /// Read-write values (empty)
437 pub mod RW {}
438 }
439
440 /// OUT endpoint interrupt bits
441 pub mod OEPINT {
442 /// Offset (16 bits)
443 pub const offset: u32 = 16;
444 /// Mask (16 bits: 0xffff << 16)
445 pub const mask: u32 = 0xffff << offset;
446 /// Read-only values (empty)
447 pub mod R {}
448 /// Write-only values (empty)
449 pub mod W {}
450 /// Read-write values (empty)
451 pub mod RW {}
452 }
453}
454
455/// OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
456pub mod DAINTMSK {
457
458 /// IN EP interrupt mask bits
459 pub mod IEPM {
460 /// Offset (0 bits)
461 pub const offset: u32 = 0;
462 /// Mask (16 bits: 0xffff << 0)
463 pub const mask: u32 = 0xffff << offset;
464 /// Read-only values (empty)
465 pub mod R {}
466 /// Write-only values (empty)
467 pub mod W {}
468 /// Read-write values (empty)
469 pub mod RW {}
470 }
471
472 /// OUT EP interrupt mask bits
473 pub mod OEPM {
474 /// Offset (16 bits)
475 pub const offset: u32 = 16;
476 /// Mask (16 bits: 0xffff << 16)
477 pub const mask: u32 = 0xffff << offset;
478 /// Read-only values (empty)
479 pub mod R {}
480 /// Write-only values (empty)
481 pub mod W {}
482 /// Read-write values (empty)
483 pub mod RW {}
484 }
485}
486
487/// OTG_FS device VBUS discharge time register
488pub mod DVBUSDIS {
489
490 /// Device VBUS discharge time
491 pub mod VBUSDT {
492 /// Offset (0 bits)
493 pub const offset: u32 = 0;
494 /// Mask (16 bits: 0xffff << 0)
495 pub const mask: u32 = 0xffff << offset;
496 /// Read-only values (empty)
497 pub mod R {}
498 /// Write-only values (empty)
499 pub mod W {}
500 /// Read-write values (empty)
501 pub mod RW {}
502 }
503}
504
505/// OTG_FS device VBUS pulsing time register
506pub mod DVBUSPULSE {
507
508 /// Device VBUS pulsing time
509 pub mod DVBUSP {
510 /// Offset (0 bits)
511 pub const offset: u32 = 0;
512 /// Mask (12 bits: 0xfff << 0)
513 pub const mask: u32 = 0xfff << offset;
514 /// Read-only values (empty)
515 pub mod R {}
516 /// Write-only values (empty)
517 pub mod W {}
518 /// Read-write values (empty)
519 pub mod RW {}
520 }
521}
522
523/// OTG_FS device IN endpoint FIFO empty interrupt mask register
524pub mod DIEPEMPMSK {
525
526 /// IN EP Tx FIFO empty interrupt mask bits
527 pub mod INEPTXFEM {
528 /// Offset (0 bits)
529 pub const offset: u32 = 0;
530 /// Mask (16 bits: 0xffff << 0)
531 pub const mask: u32 = 0xffff << offset;
532 /// Read-only values (empty)
533 pub mod R {}
534 /// Write-only values (empty)
535 pub mod W {}
536 /// Read-write values (empty)
537 pub mod RW {}
538 }
539}
540
541/// OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
542pub mod DIEPCTL0 {
543
544 /// Maximum packet size
545 pub mod MPSIZ {
546 /// Offset (0 bits)
547 pub const offset: u32 = 0;
548 /// Mask (2 bits: 0b11 << 0)
549 pub const mask: u32 = 0b11 << offset;
550 /// Read-only values (empty)
551 pub mod R {}
552 /// Write-only values (empty)
553 pub mod W {}
554 /// Read-write values (empty)
555 pub mod RW {}
556 }
557
558 /// USB active endpoint
559 pub mod USBAEP {
560 /// Offset (15 bits)
561 pub const offset: u32 = 15;
562 /// Mask (1 bit: 1 << 15)
563 pub const mask: u32 = 1 << offset;
564 /// Read-only values (empty)
565 pub mod R {}
566 /// Write-only values (empty)
567 pub mod W {}
568 /// Read-write values (empty)
569 pub mod RW {}
570 }
571
572 /// NAK status
573 pub mod NAKSTS {
574 /// Offset (17 bits)
575 pub const offset: u32 = 17;
576 /// Mask (1 bit: 1 << 17)
577 pub const mask: u32 = 1 << offset;
578 /// Read-only values (empty)
579 pub mod R {}
580 /// Write-only values (empty)
581 pub mod W {}
582 /// Read-write values (empty)
583 pub mod RW {}
584 }
585
586 /// Endpoint type
587 pub mod EPTYP {
588 /// Offset (18 bits)
589 pub const offset: u32 = 18;
590 /// Mask (2 bits: 0b11 << 18)
591 pub const mask: u32 = 0b11 << offset;
592 /// Read-only values (empty)
593 pub mod R {}
594 /// Write-only values (empty)
595 pub mod W {}
596 /// Read-write values (empty)
597 pub mod RW {}
598 }
599
600 /// STALL handshake
601 pub mod STALL {
602 /// Offset (21 bits)
603 pub const offset: u32 = 21;
604 /// Mask (1 bit: 1 << 21)
605 pub const mask: u32 = 1 << offset;
606 /// Read-only values (empty)
607 pub mod R {}
608 /// Write-only values (empty)
609 pub mod W {}
610 /// Read-write values (empty)
611 pub mod RW {}
612 }
613
614 /// TxFIFO number
615 pub mod TXFNUM {
616 /// Offset (22 bits)
617 pub const offset: u32 = 22;
618 /// Mask (4 bits: 0b1111 << 22)
619 pub const mask: u32 = 0b1111 << offset;
620 /// Read-only values (empty)
621 pub mod R {}
622 /// Write-only values (empty)
623 pub mod W {}
624 /// Read-write values (empty)
625 pub mod RW {}
626 }
627
628 /// Clear NAK
629 pub mod CNAK {
630 /// Offset (26 bits)
631 pub const offset: u32 = 26;
632 /// Mask (1 bit: 1 << 26)
633 pub const mask: u32 = 1 << offset;
634 /// Read-only values (empty)
635 pub mod R {}
636 /// Write-only values (empty)
637 pub mod W {}
638 /// Read-write values (empty)
639 pub mod RW {}
640 }
641
642 /// Set NAK
643 pub mod SNAK {
644 /// Offset (27 bits)
645 pub const offset: u32 = 27;
646 /// Mask (1 bit: 1 << 27)
647 pub const mask: u32 = 1 << offset;
648 /// Read-only values (empty)
649 pub mod R {}
650 /// Write-only values (empty)
651 pub mod W {}
652 /// Read-write values (empty)
653 pub mod RW {}
654 }
655
656 /// Endpoint disable
657 pub mod EPDIS {
658 /// Offset (30 bits)
659 pub const offset: u32 = 30;
660 /// Mask (1 bit: 1 << 30)
661 pub const mask: u32 = 1 << offset;
662 /// Read-only values (empty)
663 pub mod R {}
664 /// Write-only values (empty)
665 pub mod W {}
666 /// Read-write values (empty)
667 pub mod RW {}
668 }
669
670 /// Endpoint enable
671 pub mod EPENA {
672 /// Offset (31 bits)
673 pub const offset: u32 = 31;
674 /// Mask (1 bit: 1 << 31)
675 pub const mask: u32 = 1 << offset;
676 /// Read-only values (empty)
677 pub mod R {}
678 /// Write-only values (empty)
679 pub mod W {}
680 /// Read-write values (empty)
681 pub mod RW {}
682 }
683}
684
685/// OTG device endpoint-1 control register
686pub mod DIEPCTL1 {
687
688 /// EPENA
689 pub mod EPENA {
690 /// Offset (31 bits)
691 pub const offset: u32 = 31;
692 /// Mask (1 bit: 1 << 31)
693 pub const mask: u32 = 1 << offset;
694 /// Read-only values (empty)
695 pub mod R {}
696 /// Write-only values (empty)
697 pub mod W {}
698 /// Read-write values (empty)
699 pub mod RW {}
700 }
701
702 /// EPDIS
703 pub mod EPDIS {
704 /// Offset (30 bits)
705 pub const offset: u32 = 30;
706 /// Mask (1 bit: 1 << 30)
707 pub const mask: u32 = 1 << offset;
708 /// Read-only values (empty)
709 pub mod R {}
710 /// Write-only values (empty)
711 pub mod W {}
712 /// Read-write values (empty)
713 pub mod RW {}
714 }
715
716 /// SODDFRM/SD1PID
717 pub mod SODDFRM_SD1PID {
718 /// Offset (29 bits)
719 pub const offset: u32 = 29;
720 /// Mask (1 bit: 1 << 29)
721 pub const mask: u32 = 1 << offset;
722 /// Read-only values (empty)
723 pub mod R {}
724 /// Write-only values (empty)
725 pub mod W {}
726 /// Read-write values (empty)
727 pub mod RW {}
728 }
729
730 /// SD0PID/SEVNFRM
731 pub mod SD0PID_SEVNFRM {
732 /// Offset (28 bits)
733 pub const offset: u32 = 28;
734 /// Mask (1 bit: 1 << 28)
735 pub const mask: u32 = 1 << offset;
736 /// Read-only values (empty)
737 pub mod R {}
738 /// Write-only values (empty)
739 pub mod W {}
740 /// Read-write values (empty)
741 pub mod RW {}
742 }
743
744 /// SNAK
745 pub mod SNAK {
746 /// Offset (27 bits)
747 pub const offset: u32 = 27;
748 /// Mask (1 bit: 1 << 27)
749 pub const mask: u32 = 1 << offset;
750 /// Read-only values (empty)
751 pub mod R {}
752 /// Write-only values (empty)
753 pub mod W {}
754 /// Read-write values (empty)
755 pub mod RW {}
756 }
757
758 /// CNAK
759 pub mod CNAK {
760 /// Offset (26 bits)
761 pub const offset: u32 = 26;
762 /// Mask (1 bit: 1 << 26)
763 pub const mask: u32 = 1 << offset;
764 /// Read-only values (empty)
765 pub mod R {}
766 /// Write-only values (empty)
767 pub mod W {}
768 /// Read-write values (empty)
769 pub mod RW {}
770 }
771
772 /// TXFNUM
773 pub mod TXFNUM {
774 /// Offset (22 bits)
775 pub const offset: u32 = 22;
776 /// Mask (4 bits: 0b1111 << 22)
777 pub const mask: u32 = 0b1111 << offset;
778 /// Read-only values (empty)
779 pub mod R {}
780 /// Write-only values (empty)
781 pub mod W {}
782 /// Read-write values (empty)
783 pub mod RW {}
784 }
785
786 /// STALL
787 pub mod STALL {
788 /// Offset (21 bits)
789 pub const offset: u32 = 21;
790 /// Mask (1 bit: 1 << 21)
791 pub const mask: u32 = 1 << offset;
792 /// Read-only values (empty)
793 pub mod R {}
794 /// Write-only values (empty)
795 pub mod W {}
796 /// Read-write values (empty)
797 pub mod RW {}
798 }
799
800 /// EPTYP
801 pub mod EPTYP {
802 /// Offset (18 bits)
803 pub const offset: u32 = 18;
804 /// Mask (2 bits: 0b11 << 18)
805 pub const mask: u32 = 0b11 << offset;
806 /// Read-only values (empty)
807 pub mod R {}
808 /// Write-only values (empty)
809 pub mod W {}
810 /// Read-write values (empty)
811 pub mod RW {}
812 }
813
814 /// NAKSTS
815 pub mod NAKSTS {
816 /// Offset (17 bits)
817 pub const offset: u32 = 17;
818 /// Mask (1 bit: 1 << 17)
819 pub const mask: u32 = 1 << offset;
820 /// Read-only values (empty)
821 pub mod R {}
822 /// Write-only values (empty)
823 pub mod W {}
824 /// Read-write values (empty)
825 pub mod RW {}
826 }
827
828 /// EONUM/DPID
829 pub mod EONUM_DPID {
830 /// Offset (16 bits)
831 pub const offset: u32 = 16;
832 /// Mask (1 bit: 1 << 16)
833 pub const mask: u32 = 1 << offset;
834 /// Read-only values (empty)
835 pub mod R {}
836 /// Write-only values (empty)
837 pub mod W {}
838 /// Read-write values (empty)
839 pub mod RW {}
840 }
841
842 /// USBAEP
843 pub mod USBAEP {
844 /// Offset (15 bits)
845 pub const offset: u32 = 15;
846 /// Mask (1 bit: 1 << 15)
847 pub const mask: u32 = 1 << offset;
848 /// Read-only values (empty)
849 pub mod R {}
850 /// Write-only values (empty)
851 pub mod W {}
852 /// Read-write values (empty)
853 pub mod RW {}
854 }
855
856 /// MPSIZ
857 pub mod MPSIZ {
858 /// Offset (0 bits)
859 pub const offset: u32 = 0;
860 /// Mask (11 bits: 0x7ff << 0)
861 pub const mask: u32 = 0x7ff << offset;
862 /// Read-only values (empty)
863 pub mod R {}
864 /// Write-only values (empty)
865 pub mod W {}
866 /// Read-write values (empty)
867 pub mod RW {}
868 }
869}
870
871/// OTG device endpoint-1 control register
872pub mod DIEPCTL2 {
873 pub use super::DIEPCTL1::CNAK;
874 pub use super::DIEPCTL1::EONUM_DPID;
875 pub use super::DIEPCTL1::EPDIS;
876 pub use super::DIEPCTL1::EPENA;
877 pub use super::DIEPCTL1::EPTYP;
878 pub use super::DIEPCTL1::MPSIZ;
879 pub use super::DIEPCTL1::NAKSTS;
880 pub use super::DIEPCTL1::SD0PID_SEVNFRM;
881 pub use super::DIEPCTL1::SNAK;
882 pub use super::DIEPCTL1::SODDFRM_SD1PID;
883 pub use super::DIEPCTL1::STALL;
884 pub use super::DIEPCTL1::TXFNUM;
885 pub use super::DIEPCTL1::USBAEP;
886}
887
888/// OTG device endpoint-1 control register
889pub mod DIEPCTL3 {
890 pub use super::DIEPCTL1::CNAK;
891 pub use super::DIEPCTL1::EONUM_DPID;
892 pub use super::DIEPCTL1::EPDIS;
893 pub use super::DIEPCTL1::EPENA;
894 pub use super::DIEPCTL1::EPTYP;
895 pub use super::DIEPCTL1::MPSIZ;
896 pub use super::DIEPCTL1::NAKSTS;
897 pub use super::DIEPCTL1::SD0PID_SEVNFRM;
898 pub use super::DIEPCTL1::SNAK;
899 pub use super::DIEPCTL1::SODDFRM_SD1PID;
900 pub use super::DIEPCTL1::STALL;
901 pub use super::DIEPCTL1::TXFNUM;
902 pub use super::DIEPCTL1::USBAEP;
903}
904
905/// device endpoint-0 control register
906pub mod DOEPCTL0 {
907
908 /// EPENA
909 pub mod EPENA {
910 /// Offset (31 bits)
911 pub const offset: u32 = 31;
912 /// Mask (1 bit: 1 << 31)
913 pub const mask: u32 = 1 << offset;
914 /// Read-only values (empty)
915 pub mod R {}
916 /// Write-only values (empty)
917 pub mod W {}
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// EPDIS
923 pub mod EPDIS {
924 /// Offset (30 bits)
925 pub const offset: u32 = 30;
926 /// Mask (1 bit: 1 << 30)
927 pub const mask: u32 = 1 << offset;
928 /// Read-only values (empty)
929 pub mod R {}
930 /// Write-only values (empty)
931 pub mod W {}
932 /// Read-write values (empty)
933 pub mod RW {}
934 }
935
936 /// SNAK
937 pub mod SNAK {
938 /// Offset (27 bits)
939 pub const offset: u32 = 27;
940 /// Mask (1 bit: 1 << 27)
941 pub const mask: u32 = 1 << offset;
942 /// Read-only values (empty)
943 pub mod R {}
944 /// Write-only values (empty)
945 pub mod W {}
946 /// Read-write values (empty)
947 pub mod RW {}
948 }
949
950 /// CNAK
951 pub mod CNAK {
952 /// Offset (26 bits)
953 pub const offset: u32 = 26;
954 /// Mask (1 bit: 1 << 26)
955 pub const mask: u32 = 1 << offset;
956 /// Read-only values (empty)
957 pub mod R {}
958 /// Write-only values (empty)
959 pub mod W {}
960 /// Read-write values (empty)
961 pub mod RW {}
962 }
963
964 /// STALL
965 pub mod STALL {
966 /// Offset (21 bits)
967 pub const offset: u32 = 21;
968 /// Mask (1 bit: 1 << 21)
969 pub const mask: u32 = 1 << offset;
970 /// Read-only values (empty)
971 pub mod R {}
972 /// Write-only values (empty)
973 pub mod W {}
974 /// Read-write values (empty)
975 pub mod RW {}
976 }
977
978 /// SNPM
979 pub mod SNPM {
980 /// Offset (20 bits)
981 pub const offset: u32 = 20;
982 /// Mask (1 bit: 1 << 20)
983 pub const mask: u32 = 1 << offset;
984 /// Read-only values (empty)
985 pub mod R {}
986 /// Write-only values (empty)
987 pub mod W {}
988 /// Read-write values (empty)
989 pub mod RW {}
990 }
991
992 /// EPTYP
993 pub mod EPTYP {
994 /// Offset (18 bits)
995 pub const offset: u32 = 18;
996 /// Mask (2 bits: 0b11 << 18)
997 pub const mask: u32 = 0b11 << offset;
998 /// Read-only values (empty)
999 pub mod R {}
1000 /// Write-only values (empty)
1001 pub mod W {}
1002 /// Read-write values (empty)
1003 pub mod RW {}
1004 }
1005
1006 /// NAKSTS
1007 pub mod NAKSTS {
1008 /// Offset (17 bits)
1009 pub const offset: u32 = 17;
1010 /// Mask (1 bit: 1 << 17)
1011 pub const mask: u32 = 1 << offset;
1012 /// Read-only values (empty)
1013 pub mod R {}
1014 /// Write-only values (empty)
1015 pub mod W {}
1016 /// Read-write values (empty)
1017 pub mod RW {}
1018 }
1019
1020 /// USBAEP
1021 pub mod USBAEP {
1022 /// Offset (15 bits)
1023 pub const offset: u32 = 15;
1024 /// Mask (1 bit: 1 << 15)
1025 pub const mask: u32 = 1 << offset;
1026 /// Read-only values (empty)
1027 pub mod R {}
1028 /// Write-only values (empty)
1029 pub mod W {}
1030 /// Read-write values (empty)
1031 pub mod RW {}
1032 }
1033
1034 /// MPSIZ
1035 pub mod MPSIZ {
1036 /// Offset (0 bits)
1037 pub const offset: u32 = 0;
1038 /// Mask (2 bits: 0b11 << 0)
1039 pub const mask: u32 = 0b11 << offset;
1040 /// Read-only values (empty)
1041 pub mod R {}
1042 /// Write-only values (empty)
1043 pub mod W {}
1044 /// Read-write values (empty)
1045 pub mod RW {}
1046 }
1047}
1048
1049/// device endpoint-1 control register
1050pub mod DOEPCTL1 {
1051
1052 /// EPENA
1053 pub mod EPENA {
1054 /// Offset (31 bits)
1055 pub const offset: u32 = 31;
1056 /// Mask (1 bit: 1 << 31)
1057 pub const mask: u32 = 1 << offset;
1058 /// Read-only values (empty)
1059 pub mod R {}
1060 /// Write-only values (empty)
1061 pub mod W {}
1062 /// Read-write values (empty)
1063 pub mod RW {}
1064 }
1065
1066 /// EPDIS
1067 pub mod EPDIS {
1068 /// Offset (30 bits)
1069 pub const offset: u32 = 30;
1070 /// Mask (1 bit: 1 << 30)
1071 pub const mask: u32 = 1 << offset;
1072 /// Read-only values (empty)
1073 pub mod R {}
1074 /// Write-only values (empty)
1075 pub mod W {}
1076 /// Read-write values (empty)
1077 pub mod RW {}
1078 }
1079
1080 /// SODDFRM
1081 pub mod SODDFRM {
1082 /// Offset (29 bits)
1083 pub const offset: u32 = 29;
1084 /// Mask (1 bit: 1 << 29)
1085 pub const mask: u32 = 1 << offset;
1086 /// Read-only values (empty)
1087 pub mod R {}
1088 /// Write-only values (empty)
1089 pub mod W {}
1090 /// Read-write values (empty)
1091 pub mod RW {}
1092 }
1093
1094 /// SD0PID/SEVNFRM
1095 pub mod SD0PID_SEVNFRM {
1096 /// Offset (28 bits)
1097 pub const offset: u32 = 28;
1098 /// Mask (1 bit: 1 << 28)
1099 pub const mask: u32 = 1 << offset;
1100 /// Read-only values (empty)
1101 pub mod R {}
1102 /// Write-only values (empty)
1103 pub mod W {}
1104 /// Read-write values (empty)
1105 pub mod RW {}
1106 }
1107
1108 /// SNAK
1109 pub mod SNAK {
1110 /// Offset (27 bits)
1111 pub const offset: u32 = 27;
1112 /// Mask (1 bit: 1 << 27)
1113 pub const mask: u32 = 1 << offset;
1114 /// Read-only values (empty)
1115 pub mod R {}
1116 /// Write-only values (empty)
1117 pub mod W {}
1118 /// Read-write values (empty)
1119 pub mod RW {}
1120 }
1121
1122 /// CNAK
1123 pub mod CNAK {
1124 /// Offset (26 bits)
1125 pub const offset: u32 = 26;
1126 /// Mask (1 bit: 1 << 26)
1127 pub const mask: u32 = 1 << offset;
1128 /// Read-only values (empty)
1129 pub mod R {}
1130 /// Write-only values (empty)
1131 pub mod W {}
1132 /// Read-write values (empty)
1133 pub mod RW {}
1134 }
1135
1136 /// STALL
1137 pub mod STALL {
1138 /// Offset (21 bits)
1139 pub const offset: u32 = 21;
1140 /// Mask (1 bit: 1 << 21)
1141 pub const mask: u32 = 1 << offset;
1142 /// Read-only values (empty)
1143 pub mod R {}
1144 /// Write-only values (empty)
1145 pub mod W {}
1146 /// Read-write values (empty)
1147 pub mod RW {}
1148 }
1149
1150 /// SNPM
1151 pub mod SNPM {
1152 /// Offset (20 bits)
1153 pub const offset: u32 = 20;
1154 /// Mask (1 bit: 1 << 20)
1155 pub const mask: u32 = 1 << offset;
1156 /// Read-only values (empty)
1157 pub mod R {}
1158 /// Write-only values (empty)
1159 pub mod W {}
1160 /// Read-write values (empty)
1161 pub mod RW {}
1162 }
1163
1164 /// EPTYP
1165 pub mod EPTYP {
1166 /// Offset (18 bits)
1167 pub const offset: u32 = 18;
1168 /// Mask (2 bits: 0b11 << 18)
1169 pub const mask: u32 = 0b11 << offset;
1170 /// Read-only values (empty)
1171 pub mod R {}
1172 /// Write-only values (empty)
1173 pub mod W {}
1174 /// Read-write values (empty)
1175 pub mod RW {}
1176 }
1177
1178 /// NAKSTS
1179 pub mod NAKSTS {
1180 /// Offset (17 bits)
1181 pub const offset: u32 = 17;
1182 /// Mask (1 bit: 1 << 17)
1183 pub const mask: u32 = 1 << offset;
1184 /// Read-only values (empty)
1185 pub mod R {}
1186 /// Write-only values (empty)
1187 pub mod W {}
1188 /// Read-write values (empty)
1189 pub mod RW {}
1190 }
1191
1192 /// EONUM/DPID
1193 pub mod EONUM_DPID {
1194 /// Offset (16 bits)
1195 pub const offset: u32 = 16;
1196 /// Mask (1 bit: 1 << 16)
1197 pub const mask: u32 = 1 << offset;
1198 /// Read-only values (empty)
1199 pub mod R {}
1200 /// Write-only values (empty)
1201 pub mod W {}
1202 /// Read-write values (empty)
1203 pub mod RW {}
1204 }
1205
1206 /// USBAEP
1207 pub mod USBAEP {
1208 /// Offset (15 bits)
1209 pub const offset: u32 = 15;
1210 /// Mask (1 bit: 1 << 15)
1211 pub const mask: u32 = 1 << offset;
1212 /// Read-only values (empty)
1213 pub mod R {}
1214 /// Write-only values (empty)
1215 pub mod W {}
1216 /// Read-write values (empty)
1217 pub mod RW {}
1218 }
1219
1220 /// MPSIZ
1221 pub mod MPSIZ {
1222 /// Offset (0 bits)
1223 pub const offset: u32 = 0;
1224 /// Mask (11 bits: 0x7ff << 0)
1225 pub const mask: u32 = 0x7ff << offset;
1226 /// Read-only values (empty)
1227 pub mod R {}
1228 /// Write-only values (empty)
1229 pub mod W {}
1230 /// Read-write values (empty)
1231 pub mod RW {}
1232 }
1233}
1234
1235/// device endpoint-1 control register
1236pub mod DOEPCTL2 {
1237 pub use super::DOEPCTL1::CNAK;
1238 pub use super::DOEPCTL1::EONUM_DPID;
1239 pub use super::DOEPCTL1::EPDIS;
1240 pub use super::DOEPCTL1::EPENA;
1241 pub use super::DOEPCTL1::EPTYP;
1242 pub use super::DOEPCTL1::MPSIZ;
1243 pub use super::DOEPCTL1::NAKSTS;
1244 pub use super::DOEPCTL1::SD0PID_SEVNFRM;
1245 pub use super::DOEPCTL1::SNAK;
1246 pub use super::DOEPCTL1::SNPM;
1247 pub use super::DOEPCTL1::SODDFRM;
1248 pub use super::DOEPCTL1::STALL;
1249 pub use super::DOEPCTL1::USBAEP;
1250}
1251
1252/// device endpoint-1 control register
1253pub mod DOEPCTL3 {
1254 pub use super::DOEPCTL1::CNAK;
1255 pub use super::DOEPCTL1::EONUM_DPID;
1256 pub use super::DOEPCTL1::EPDIS;
1257 pub use super::DOEPCTL1::EPENA;
1258 pub use super::DOEPCTL1::EPTYP;
1259 pub use super::DOEPCTL1::MPSIZ;
1260 pub use super::DOEPCTL1::NAKSTS;
1261 pub use super::DOEPCTL1::SD0PID_SEVNFRM;
1262 pub use super::DOEPCTL1::SNAK;
1263 pub use super::DOEPCTL1::SNPM;
1264 pub use super::DOEPCTL1::SODDFRM;
1265 pub use super::DOEPCTL1::STALL;
1266 pub use super::DOEPCTL1::USBAEP;
1267}
1268
1269/// device endpoint-x interrupt register
1270pub mod DIEPINT0 {
1271
1272 /// TXFE
1273 pub mod TXFE {
1274 /// Offset (7 bits)
1275 pub const offset: u32 = 7;
1276 /// Mask (1 bit: 1 << 7)
1277 pub const mask: u32 = 1 << offset;
1278 /// Read-only values (empty)
1279 pub mod R {}
1280 /// Write-only values (empty)
1281 pub mod W {}
1282 /// Read-write values (empty)
1283 pub mod RW {}
1284 }
1285
1286 /// INEPNE
1287 pub mod INEPNE {
1288 /// Offset (6 bits)
1289 pub const offset: u32 = 6;
1290 /// Mask (1 bit: 1 << 6)
1291 pub const mask: u32 = 1 << offset;
1292 /// Read-only values (empty)
1293 pub mod R {}
1294 /// Write-only values (empty)
1295 pub mod W {}
1296 /// Read-write values (empty)
1297 pub mod RW {}
1298 }
1299
1300 /// ITTXFE
1301 pub mod ITTXFE {
1302 /// Offset (4 bits)
1303 pub const offset: u32 = 4;
1304 /// Mask (1 bit: 1 << 4)
1305 pub const mask: u32 = 1 << offset;
1306 /// Read-only values (empty)
1307 pub mod R {}
1308 /// Write-only values (empty)
1309 pub mod W {}
1310 /// Read-write values (empty)
1311 pub mod RW {}
1312 }
1313
1314 /// TOC
1315 pub mod TOC {
1316 /// Offset (3 bits)
1317 pub const offset: u32 = 3;
1318 /// Mask (1 bit: 1 << 3)
1319 pub const mask: u32 = 1 << offset;
1320 /// Read-only values (empty)
1321 pub mod R {}
1322 /// Write-only values (empty)
1323 pub mod W {}
1324 /// Read-write values (empty)
1325 pub mod RW {}
1326 }
1327
1328 /// EPDISD
1329 pub mod EPDISD {
1330 /// Offset (1 bits)
1331 pub const offset: u32 = 1;
1332 /// Mask (1 bit: 1 << 1)
1333 pub const mask: u32 = 1 << offset;
1334 /// Read-only values (empty)
1335 pub mod R {}
1336 /// Write-only values (empty)
1337 pub mod W {}
1338 /// Read-write values (empty)
1339 pub mod RW {}
1340 }
1341
1342 /// XFRC
1343 pub mod XFRC {
1344 /// Offset (0 bits)
1345 pub const offset: u32 = 0;
1346 /// Mask (1 bit: 1 << 0)
1347 pub const mask: u32 = 1 << offset;
1348 /// Read-only values (empty)
1349 pub mod R {}
1350 /// Write-only values (empty)
1351 pub mod W {}
1352 /// Read-write values (empty)
1353 pub mod RW {}
1354 }
1355}
1356
1357/// device endpoint-1 interrupt register
1358pub mod DIEPINT1 {
1359 pub use super::DIEPINT0::EPDISD;
1360 pub use super::DIEPINT0::INEPNE;
1361 pub use super::DIEPINT0::ITTXFE;
1362 pub use super::DIEPINT0::TOC;
1363 pub use super::DIEPINT0::TXFE;
1364 pub use super::DIEPINT0::XFRC;
1365}
1366
1367/// device endpoint-2 interrupt register
1368pub mod DIEPINT2 {
1369 pub use super::DIEPINT0::EPDISD;
1370 pub use super::DIEPINT0::INEPNE;
1371 pub use super::DIEPINT0::ITTXFE;
1372 pub use super::DIEPINT0::TOC;
1373 pub use super::DIEPINT0::TXFE;
1374 pub use super::DIEPINT0::XFRC;
1375}
1376
1377/// device endpoint-3 interrupt register
1378pub mod DIEPINT3 {
1379 pub use super::DIEPINT0::EPDISD;
1380 pub use super::DIEPINT0::INEPNE;
1381 pub use super::DIEPINT0::ITTXFE;
1382 pub use super::DIEPINT0::TOC;
1383 pub use super::DIEPINT0::TXFE;
1384 pub use super::DIEPINT0::XFRC;
1385}
1386
1387/// device endpoint-0 interrupt register
1388pub mod DOEPINT0 {
1389
1390 /// B2BSTUP
1391 pub mod B2BSTUP {
1392 /// Offset (6 bits)
1393 pub const offset: u32 = 6;
1394 /// Mask (1 bit: 1 << 6)
1395 pub const mask: u32 = 1 << offset;
1396 /// Read-only values (empty)
1397 pub mod R {}
1398 /// Write-only values (empty)
1399 pub mod W {}
1400 /// Read-write values (empty)
1401 pub mod RW {}
1402 }
1403
1404 /// OTEPDIS
1405 pub mod OTEPDIS {
1406 /// Offset (4 bits)
1407 pub const offset: u32 = 4;
1408 /// Mask (1 bit: 1 << 4)
1409 pub const mask: u32 = 1 << offset;
1410 /// Read-only values (empty)
1411 pub mod R {}
1412 /// Write-only values (empty)
1413 pub mod W {}
1414 /// Read-write values (empty)
1415 pub mod RW {}
1416 }
1417
1418 /// STUP
1419 pub mod STUP {
1420 /// Offset (3 bits)
1421 pub const offset: u32 = 3;
1422 /// Mask (1 bit: 1 << 3)
1423 pub const mask: u32 = 1 << offset;
1424 /// Read-only values (empty)
1425 pub mod R {}
1426 /// Write-only values (empty)
1427 pub mod W {}
1428 /// Read-write values (empty)
1429 pub mod RW {}
1430 }
1431
1432 /// EPDISD
1433 pub mod EPDISD {
1434 /// Offset (1 bits)
1435 pub const offset: u32 = 1;
1436 /// Mask (1 bit: 1 << 1)
1437 pub const mask: u32 = 1 << offset;
1438 /// Read-only values (empty)
1439 pub mod R {}
1440 /// Write-only values (empty)
1441 pub mod W {}
1442 /// Read-write values (empty)
1443 pub mod RW {}
1444 }
1445
1446 /// XFRC
1447 pub mod XFRC {
1448 /// Offset (0 bits)
1449 pub const offset: u32 = 0;
1450 /// Mask (1 bit: 1 << 0)
1451 pub const mask: u32 = 1 << offset;
1452 /// Read-only values (empty)
1453 pub mod R {}
1454 /// Write-only values (empty)
1455 pub mod W {}
1456 /// Read-write values (empty)
1457 pub mod RW {}
1458 }
1459}
1460
1461/// device endpoint-1 interrupt register
1462pub mod DOEPINT1 {
1463 pub use super::DOEPINT0::B2BSTUP;
1464 pub use super::DOEPINT0::EPDISD;
1465 pub use super::DOEPINT0::OTEPDIS;
1466 pub use super::DOEPINT0::STUP;
1467 pub use super::DOEPINT0::XFRC;
1468}
1469
1470/// device endpoint-2 interrupt register
1471pub mod DOEPINT2 {
1472 pub use super::DOEPINT0::B2BSTUP;
1473 pub use super::DOEPINT0::EPDISD;
1474 pub use super::DOEPINT0::OTEPDIS;
1475 pub use super::DOEPINT0::STUP;
1476 pub use super::DOEPINT0::XFRC;
1477}
1478
1479/// device endpoint-3 interrupt register
1480pub mod DOEPINT3 {
1481 pub use super::DOEPINT0::B2BSTUP;
1482 pub use super::DOEPINT0::EPDISD;
1483 pub use super::DOEPINT0::OTEPDIS;
1484 pub use super::DOEPINT0::STUP;
1485 pub use super::DOEPINT0::XFRC;
1486}
1487
1488/// device endpoint-0 transfer size register
1489pub mod DIEPTSIZ0 {
1490
1491 /// Packet count
1492 pub mod PKTCNT {
1493 /// Offset (19 bits)
1494 pub const offset: u32 = 19;
1495 /// Mask (2 bits: 0b11 << 19)
1496 pub const mask: u32 = 0b11 << offset;
1497 /// Read-only values (empty)
1498 pub mod R {}
1499 /// Write-only values (empty)
1500 pub mod W {}
1501 /// Read-write values (empty)
1502 pub mod RW {}
1503 }
1504
1505 /// Transfer size
1506 pub mod XFRSIZ {
1507 /// Offset (0 bits)
1508 pub const offset: u32 = 0;
1509 /// Mask (7 bits: 0x7f << 0)
1510 pub const mask: u32 = 0x7f << offset;
1511 /// Read-only values (empty)
1512 pub mod R {}
1513 /// Write-only values (empty)
1514 pub mod W {}
1515 /// Read-write values (empty)
1516 pub mod RW {}
1517 }
1518}
1519
1520/// device OUT endpoint-0 transfer size register
1521pub mod DOEPTSIZ0 {
1522
1523 /// SETUP packet count
1524 pub mod STUPCNT {
1525 /// Offset (29 bits)
1526 pub const offset: u32 = 29;
1527 /// Mask (2 bits: 0b11 << 29)
1528 pub const mask: u32 = 0b11 << offset;
1529 /// Read-only values (empty)
1530 pub mod R {}
1531 /// Write-only values (empty)
1532 pub mod W {}
1533 /// Read-write values (empty)
1534 pub mod RW {}
1535 }
1536
1537 /// Packet count
1538 pub mod PKTCNT {
1539 /// Offset (19 bits)
1540 pub const offset: u32 = 19;
1541 /// Mask (1 bit: 1 << 19)
1542 pub const mask: u32 = 1 << offset;
1543 /// Read-only values (empty)
1544 pub mod R {}
1545 /// Write-only values (empty)
1546 pub mod W {}
1547 /// Read-write values (empty)
1548 pub mod RW {}
1549 }
1550
1551 /// Transfer size
1552 pub mod XFRSIZ {
1553 /// Offset (0 bits)
1554 pub const offset: u32 = 0;
1555 /// Mask (7 bits: 0x7f << 0)
1556 pub const mask: u32 = 0x7f << offset;
1557 /// Read-only values (empty)
1558 pub mod R {}
1559 /// Write-only values (empty)
1560 pub mod W {}
1561 /// Read-write values (empty)
1562 pub mod RW {}
1563 }
1564}
1565
1566/// device endpoint-1 transfer size register
1567pub mod DIEPTSIZ1 {
1568
1569 /// Multi count
1570 pub mod MCNT {
1571 /// Offset (29 bits)
1572 pub const offset: u32 = 29;
1573 /// Mask (2 bits: 0b11 << 29)
1574 pub const mask: u32 = 0b11 << offset;
1575 /// Read-only values (empty)
1576 pub mod R {}
1577 /// Write-only values (empty)
1578 pub mod W {}
1579 /// Read-write values (empty)
1580 pub mod RW {}
1581 }
1582
1583 /// Packet count
1584 pub mod PKTCNT {
1585 /// Offset (19 bits)
1586 pub const offset: u32 = 19;
1587 /// Mask (10 bits: 0x3ff << 19)
1588 pub const mask: u32 = 0x3ff << offset;
1589 /// Read-only values (empty)
1590 pub mod R {}
1591 /// Write-only values (empty)
1592 pub mod W {}
1593 /// Read-write values (empty)
1594 pub mod RW {}
1595 }
1596
1597 /// Transfer size
1598 pub mod XFRSIZ {
1599 /// Offset (0 bits)
1600 pub const offset: u32 = 0;
1601 /// Mask (19 bits: 0x7ffff << 0)
1602 pub const mask: u32 = 0x7ffff << offset;
1603 /// Read-only values (empty)
1604 pub mod R {}
1605 /// Write-only values (empty)
1606 pub mod W {}
1607 /// Read-write values (empty)
1608 pub mod RW {}
1609 }
1610}
1611
1612/// device endpoint-2 transfer size register
1613pub mod DIEPTSIZ2 {
1614 pub use super::DIEPTSIZ1::MCNT;
1615 pub use super::DIEPTSIZ1::PKTCNT;
1616 pub use super::DIEPTSIZ1::XFRSIZ;
1617}
1618
1619/// device endpoint-3 transfer size register
1620pub mod DIEPTSIZ3 {
1621 pub use super::DIEPTSIZ1::MCNT;
1622 pub use super::DIEPTSIZ1::PKTCNT;
1623 pub use super::DIEPTSIZ1::XFRSIZ;
1624}
1625
1626/// OTG_FS device IN endpoint transmit FIFO status register
1627pub mod DTXFSTS0 {
1628
1629 /// IN endpoint TxFIFO space available
1630 pub mod INEPTFSAV {
1631 /// Offset (0 bits)
1632 pub const offset: u32 = 0;
1633 /// Mask (16 bits: 0xffff << 0)
1634 pub const mask: u32 = 0xffff << offset;
1635 /// Read-only values (empty)
1636 pub mod R {}
1637 /// Write-only values (empty)
1638 pub mod W {}
1639 /// Read-write values (empty)
1640 pub mod RW {}
1641 }
1642}
1643
1644/// OTG_FS device IN endpoint transmit FIFO status register
1645pub mod DTXFSTS1 {
1646 pub use super::DTXFSTS0::INEPTFSAV;
1647}
1648
1649/// OTG_FS device IN endpoint transmit FIFO status register
1650pub mod DTXFSTS2 {
1651 pub use super::DTXFSTS0::INEPTFSAV;
1652}
1653
1654/// OTG_FS device IN endpoint transmit FIFO status register
1655pub mod DTXFSTS3 {
1656 pub use super::DTXFSTS0::INEPTFSAV;
1657}
1658
1659/// device OUT endpoint-1 transfer size register
1660pub mod DOEPTSIZ1 {
1661
1662 /// Received data PID/SETUP packet count
1663 pub mod RXDPID_STUPCNT {
1664 /// Offset (29 bits)
1665 pub const offset: u32 = 29;
1666 /// Mask (2 bits: 0b11 << 29)
1667 pub const mask: u32 = 0b11 << offset;
1668 /// Read-only values (empty)
1669 pub mod R {}
1670 /// Write-only values (empty)
1671 pub mod W {}
1672 /// Read-write values (empty)
1673 pub mod RW {}
1674 }
1675
1676 /// Packet count
1677 pub mod PKTCNT {
1678 /// Offset (19 bits)
1679 pub const offset: u32 = 19;
1680 /// Mask (10 bits: 0x3ff << 19)
1681 pub const mask: u32 = 0x3ff << offset;
1682 /// Read-only values (empty)
1683 pub mod R {}
1684 /// Write-only values (empty)
1685 pub mod W {}
1686 /// Read-write values (empty)
1687 pub mod RW {}
1688 }
1689
1690 /// Transfer size
1691 pub mod XFRSIZ {
1692 /// Offset (0 bits)
1693 pub const offset: u32 = 0;
1694 /// Mask (19 bits: 0x7ffff << 0)
1695 pub const mask: u32 = 0x7ffff << offset;
1696 /// Read-only values (empty)
1697 pub mod R {}
1698 /// Write-only values (empty)
1699 pub mod W {}
1700 /// Read-write values (empty)
1701 pub mod RW {}
1702 }
1703}
1704
1705/// device OUT endpoint-2 transfer size register
1706pub mod DOEPTSIZ2 {
1707 pub use super::DOEPTSIZ1::PKTCNT;
1708 pub use super::DOEPTSIZ1::RXDPID_STUPCNT;
1709 pub use super::DOEPTSIZ1::XFRSIZ;
1710}
1711
1712/// device OUT endpoint-3 transfer size register
1713pub mod DOEPTSIZ3 {
1714 pub use super::DOEPTSIZ1::PKTCNT;
1715 pub use super::DOEPTSIZ1::RXDPID_STUPCNT;
1716 pub use super::DOEPTSIZ1::XFRSIZ;
1717}
1718#[repr(C)]
1719pub struct RegisterBlock {
1720 /// OTG_FS device configuration register (OTG_FS_DCFG)
1721 pub DCFG: RWRegister<u32>,
1722
1723 /// OTG_FS device control register (OTG_FS_DCTL)
1724 pub DCTL: RWRegister<u32>,
1725
1726 /// OTG_FS device status register (OTG_FS_DSTS)
1727 pub DSTS: RORegister<u32>,
1728
1729 _reserved1: [u32; 1],
1730
1731 /// OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
1732 pub DIEPMSK: RWRegister<u32>,
1733
1734 /// OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
1735 pub DOEPMSK: RWRegister<u32>,
1736
1737 /// OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
1738 pub DAINT: RORegister<u32>,
1739
1740 /// OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
1741 pub DAINTMSK: RWRegister<u32>,
1742
1743 _reserved2: [u32; 2],
1744
1745 /// OTG_FS device VBUS discharge time register
1746 pub DVBUSDIS: RWRegister<u32>,
1747
1748 /// OTG_FS device VBUS pulsing time register
1749 pub DVBUSPULSE: RWRegister<u32>,
1750
1751 _reserved3: [u32; 1],
1752
1753 /// OTG_FS device IN endpoint FIFO empty interrupt mask register
1754 pub DIEPEMPMSK: RWRegister<u32>,
1755
1756 _reserved4: [u32; 50],
1757
1758 /// OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
1759 pub DIEPCTL0: RWRegister<u32>,
1760
1761 _reserved5: [u32; 1],
1762
1763 /// device endpoint-x interrupt register
1764 pub DIEPINT0: RWRegister<u32>,
1765
1766 _reserved6: [u32; 1],
1767
1768 /// device endpoint-0 transfer size register
1769 pub DIEPTSIZ0: RWRegister<u32>,
1770
1771 _reserved7: [u32; 1],
1772
1773 /// OTG_FS device IN endpoint transmit FIFO status register
1774 pub DTXFSTS0: RORegister<u32>,
1775
1776 _reserved8: [u32; 1],
1777
1778 /// OTG device endpoint-1 control register
1779 pub DIEPCTL1: RWRegister<u32>,
1780
1781 _reserved9: [u32; 1],
1782
1783 /// device endpoint-1 interrupt register
1784 pub DIEPINT1: RWRegister<u32>,
1785
1786 _reserved10: [u32; 1],
1787
1788 /// device endpoint-1 transfer size register
1789 pub DIEPTSIZ1: RWRegister<u32>,
1790
1791 _reserved11: [u32; 1],
1792
1793 /// OTG_FS device IN endpoint transmit FIFO status register
1794 pub DTXFSTS1: RORegister<u32>,
1795
1796 _reserved12: [u32; 1],
1797
1798 /// OTG device endpoint-1 control register
1799 pub DIEPCTL2: RWRegister<u32>,
1800
1801 _reserved13: [u32; 1],
1802
1803 /// device endpoint-2 interrupt register
1804 pub DIEPINT2: RWRegister<u32>,
1805
1806 _reserved14: [u32; 1],
1807
1808 /// device endpoint-2 transfer size register
1809 pub DIEPTSIZ2: RWRegister<u32>,
1810
1811 _reserved15: [u32; 1],
1812
1813 /// OTG_FS device IN endpoint transmit FIFO status register
1814 pub DTXFSTS2: RORegister<u32>,
1815
1816 _reserved16: [u32; 1],
1817
1818 /// OTG device endpoint-1 control register
1819 pub DIEPCTL3: RWRegister<u32>,
1820
1821 _reserved17: [u32; 1],
1822
1823 /// device endpoint-3 interrupt register
1824 pub DIEPINT3: RWRegister<u32>,
1825
1826 _reserved18: [u32; 1],
1827
1828 /// device endpoint-3 transfer size register
1829 pub DIEPTSIZ3: RWRegister<u32>,
1830
1831 _reserved19: [u32; 1],
1832
1833 /// OTG_FS device IN endpoint transmit FIFO status register
1834 pub DTXFSTS3: RORegister<u32>,
1835
1836 _reserved20: [u32; 97],
1837
1838 /// device endpoint-0 control register
1839 pub DOEPCTL0: RWRegister<u32>,
1840
1841 _reserved21: [u32; 1],
1842
1843 /// device endpoint-0 interrupt register
1844 pub DOEPINT0: RWRegister<u32>,
1845
1846 _reserved22: [u32; 1],
1847
1848 /// device OUT endpoint-0 transfer size register
1849 pub DOEPTSIZ0: RWRegister<u32>,
1850
1851 _reserved23: [u32; 3],
1852
1853 /// device endpoint-1 control register
1854 pub DOEPCTL1: RWRegister<u32>,
1855
1856 _reserved24: [u32; 1],
1857
1858 /// device endpoint-1 interrupt register
1859 pub DOEPINT1: RWRegister<u32>,
1860
1861 _reserved25: [u32; 1],
1862
1863 /// device OUT endpoint-1 transfer size register
1864 pub DOEPTSIZ1: RWRegister<u32>,
1865
1866 _reserved26: [u32; 3],
1867
1868 /// device endpoint-1 control register
1869 pub DOEPCTL2: RWRegister<u32>,
1870
1871 _reserved27: [u32; 1],
1872
1873 /// device endpoint-2 interrupt register
1874 pub DOEPINT2: RWRegister<u32>,
1875
1876 _reserved28: [u32; 1],
1877
1878 /// device OUT endpoint-2 transfer size register
1879 pub DOEPTSIZ2: RWRegister<u32>,
1880
1881 _reserved29: [u32; 3],
1882
1883 /// device endpoint-1 control register
1884 pub DOEPCTL3: RWRegister<u32>,
1885
1886 _reserved30: [u32; 1],
1887
1888 /// device endpoint-3 interrupt register
1889 pub DOEPINT3: RWRegister<u32>,
1890
1891 _reserved31: [u32; 1],
1892
1893 /// device OUT endpoint-3 transfer size register
1894 pub DOEPTSIZ3: RWRegister<u32>,
1895}
1896pub struct ResetValues {
1897 pub DCFG: u32,
1898 pub DCTL: u32,
1899 pub DSTS: u32,
1900 pub DIEPMSK: u32,
1901 pub DOEPMSK: u32,
1902 pub DAINT: u32,
1903 pub DAINTMSK: u32,
1904 pub DVBUSDIS: u32,
1905 pub DVBUSPULSE: u32,
1906 pub DIEPEMPMSK: u32,
1907 pub DIEPCTL0: u32,
1908 pub DIEPINT0: u32,
1909 pub DIEPTSIZ0: u32,
1910 pub DTXFSTS0: u32,
1911 pub DIEPCTL1: u32,
1912 pub DIEPINT1: u32,
1913 pub DIEPTSIZ1: u32,
1914 pub DTXFSTS1: u32,
1915 pub DIEPCTL2: u32,
1916 pub DIEPINT2: u32,
1917 pub DIEPTSIZ2: u32,
1918 pub DTXFSTS2: u32,
1919 pub DIEPCTL3: u32,
1920 pub DIEPINT3: u32,
1921 pub DIEPTSIZ3: u32,
1922 pub DTXFSTS3: u32,
1923 pub DOEPCTL0: u32,
1924 pub DOEPINT0: u32,
1925 pub DOEPTSIZ0: u32,
1926 pub DOEPCTL1: u32,
1927 pub DOEPINT1: u32,
1928 pub DOEPTSIZ1: u32,
1929 pub DOEPCTL2: u32,
1930 pub DOEPINT2: u32,
1931 pub DOEPTSIZ2: u32,
1932 pub DOEPCTL3: u32,
1933 pub DOEPINT3: u32,
1934 pub DOEPTSIZ3: u32,
1935}
1936#[cfg(not(feature = "nosync"))]
1937pub struct Instance {
1938 pub(crate) addr: u32,
1939 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1940}
1941#[cfg(not(feature = "nosync"))]
1942impl ::core::ops::Deref for Instance {
1943 type Target = RegisterBlock;
1944 #[inline(always)]
1945 fn deref(&self) -> &RegisterBlock {
1946 unsafe { &*(self.addr as *const _) }
1947 }
1948}
1949#[cfg(feature = "rtfm")]
1950unsafe impl Send for Instance {}