#[non_exhaustive]#[repr(u32)]pub enum CpuFamily {
Unknown,
Intel32,
Amd64,
Arm32,
Arm64,
Ppc32,
Ppc64,
Mips32,
Mips64,
Arm64_32,
Wasm32,
}
Expand description
Represents a family of CPUs.
This is strongly connected to the Arch
type, but reduces the selection to a range of
families with distinct properties, such as a generally common instruction set and pointer size.
This enumeration is represented as u32
for C-bindings and lowlevel APIs.
Variants (Non-exhaustive)§
This enum is marked as non-exhaustive
Unknown
Any other CPU family that is not explicitly supported.
Intel32
32-bit little-endian CPUs using the Intel 8086 instruction set, also known as x86
.
Amd64
64-bit little-endian, also known as x86_64
, now widely used by Intel and AMD.
Arm32
32-bit ARM.
Arm64
64-bit ARM (e.g. ARMv8-A).
Ppc32
32-bit big-endian PowerPC.
Ppc64
64-bit big-endian PowerPC.
Mips32
32-bit MIPS.
Mips64
64-bit MIPS.
Arm64_32
ILP32 ABI on 64-bit ARM.
Wasm32
Virtual WASM 32-bit architecture.
Implementations§
source§impl CpuFamily
impl CpuFamily
sourcepub fn pointer_size(self) -> Option<usize>
pub fn pointer_size(self) -> Option<usize>
Returns the native pointer size.
This commonly defines the size of CPU registers including the instruction pointer, and the size of all pointers on the platform.
This function returns None
if the CPU family is unknown.
Examples
use symbolic_common::CpuFamily;
assert_eq!(CpuFamily::Amd64.pointer_size(), Some(8));
assert_eq!(CpuFamily::Intel32.pointer_size(), Some(4));
sourcepub fn instruction_alignment(self) -> Option<u64>
pub fn instruction_alignment(self) -> Option<u64>
Returns instruction alignment if fixed.
Some instruction sets, such as Intel’s x86, use variable length instruction encoding.
Others, such as ARM, have fixed length instructions. This method returns Some
for fixed
size instructions and None
for variable-length instruction sizes.
Examples
use symbolic_common::CpuFamily;
// variable length on x86_64:
assert_eq!(CpuFamily::Amd64.instruction_alignment(), None);
// 4-byte alignment on all 64-bit ARM variants:
assert_eq!(CpuFamily::Arm64.instruction_alignment(), Some(4));
sourcepub fn ip_register_name(self) -> Option<&'static str>
pub fn ip_register_name(self) -> Option<&'static str>
Returns the name of the instruction pointer register.
The instruction pointer register holds a pointer to currrent code execution at all times.
This is a differrent register on each CPU family. The size of the value in this register is
specified by pointer_size
.
Returns None
if the CPU family is unknown.
Examples
use symbolic_common::CpuFamily;
assert_eq!(CpuFamily::Amd64.ip_register_name(), Some("rip"));
Trait Implementations§
source§impl Ord for CpuFamily
impl Ord for CpuFamily
source§impl PartialEq<CpuFamily> for CpuFamily
impl PartialEq<CpuFamily> for CpuFamily
source§impl PartialOrd<CpuFamily> for CpuFamily
impl PartialOrd<CpuFamily> for CpuFamily
1.0.0 · source§fn le(&self, other: &Rhs) -> bool
fn le(&self, other: &Rhs) -> bool
self
and other
) and is used by the <=
operator. Read moreimpl Copy for CpuFamily
impl Eq for CpuFamily
impl StructuralEq for CpuFamily
impl StructuralPartialEq for CpuFamily
Auto Trait Implementations§
impl RefUnwindSafe for CpuFamily
impl Send for CpuFamily
impl Sync for CpuFamily
impl Unpin for CpuFamily
impl UnwindSafe for CpuFamily
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