Enum symbolic_common::CpuFamily

#[repr(u32)]
#[non_exhaustive]
pub enum CpuFamily {
    Unknown,
    Intel32,
    Amd64,
    Arm32,
    Arm64,
    Ppc32,
    Ppc64,
    Mips32,
    Mips64,
    Arm64_32,
    Wasm32,
}

Represents a family of CPUs.

This is strongly connected to the Arch type, but reduces the selection to a range of families with distinct properties, such as a generally common instruction set and pointer size.

This enumeration is represented as u32 for C-bindings and lowlevel APIs.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

Unknown

Any other CPU family that is not explicitly supported.

Intel32

32-bit little-endian CPUs using the Intel 8086 instruction set, also known as x86.

Amd64

64-bit little-endian, also known as x86_64, now widely used by Intel and AMD.

Arm32

32-bit ARM.

Arm64

64-bit ARM (e.g. ARMv8-A).

Ppc32

32-bit big-endian PowerPC.

Ppc64

64-bit big-endian PowerPC.

Mips32

32-bit MIPS.

Mips64

64-bit MIPS.

Arm64_32

ILP32 ABI on 64-bit ARM.

Wasm32

Virtual WASM 32-bit architecture.

Implementations

impl CpuFamily

pub fn pointer_size(self) -> Option<usize>

Returns the native pointer size.

This commonly defines the size of CPU registers including the instruction pointer, and the size of all pointers on the platform.

This function returns None if the CPU family is unknown.

Examples

use symbolic_common::CpuFamily;

assert_eq!(CpuFamily::Amd64.pointer_size(), Some(8));
assert_eq!(CpuFamily::Intel32.pointer_size(), Some(4));

pub fn instruction_alignment(self) -> Option<u64>

Returns instruction alignment if fixed.

Some instruction sets, such as Intel’s x86, use variable length instruction encoding. Others, such as ARM, have fixed length instructions. This method returns Some for fixed size instructions and None for variable-length instruction sizes.

Examples

use symbolic_common::CpuFamily;

// variable length on x86_64:
assert_eq!(CpuFamily::Amd64.instruction_alignment(), None);

// 4-byte alignment on all 64-bit ARM variants:
assert_eq!(CpuFamily::Arm64.instruction_alignment(), Some(4));

pub fn ip_register_name(self) -> Option<&'static str>

Returns the name of the instruction pointer register.

The instruction pointer register holds a pointer to currrent code execution at all times. This is a differrent register on each CPU family. The size of the value in this register is specified by pointer_size.

Returns None if the CPU family is unknown.

Examples

use symbolic_common::CpuFamily;

assert_eq!(CpuFamily::Amd64.ip_register_name(), Some("rip"));

pub fn cfi_register_name(self, register: u16) -> Option<&'static str>

Returns the name of a register in a given architecture used in CFI programs.

Each CPU family specifies its own register sets, wherer the registers are numbered. This resolves the name of the register for the given family, if defined. Returns None if the CPU family is unknown, or the register is not defined for the family.

Note: The CFI register name differs from ip_register_name. For instance, on x86-64 the instruction pointer is returned as $rip instead of just rip. This differentiation is made to be compatible with the Google Breakpad library.

Examples

use symbolic_common::CpuFamily;

// 16 is the instruction pointer register:
assert_eq!(CpuFamily::Amd64.cfi_register_name(16), Some("$rip"));

Trait Implementations

impl Clone for CpuFamily

fn clone(&self) -> CpuFamily

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CpuFamily

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for CpuFamily

fn default() -> Self

Returns the “default value” for a type.

impl Hash for CpuFamily

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H) where
    H: Hasher, 

Feeds a slice of this type into the given Hasher.

impl Ord for CpuFamily

fn cmp(&self, other: &CpuFamily) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

Restrict a value to a certain interval.

impl PartialEq<CpuFamily> for CpuFamily

fn eq(&self, other: &CpuFamily) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl PartialOrd<CpuFamily> for CpuFamily

fn partial_cmp(&self, other: &CpuFamily) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

This method tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

This method tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

This method tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

This method tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for CpuFamily

impl Eq for CpuFamily

impl StructuralEq for CpuFamily

impl StructuralPartialEq for CpuFamily