swm341_pac/usbh/
portsr.rs1#[doc = "Register `PORTSR` reader"]
2pub struct R(crate::R<PORTSR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PORTSR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PORTSR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PORTSR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PORTSR` writer"]
17pub struct W(crate::W<PORTSR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PORTSR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PORTSR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PORTSR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CONN` reader - CONN field"]
38pub type CONN_R = crate::BitReader<bool>;
39#[doc = "Field `CONN` writer - CONN field"]
40pub type CONN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
41#[doc = "Field `ENA` reader - ENA field"]
42pub type ENA_R = crate::BitReader<bool>;
43#[doc = "Field `ENA` writer - ENA field"]
44pub type ENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
45#[doc = "Field `SUSP` reader - SUSP field"]
46pub type SUSP_R = crate::BitReader<bool>;
47#[doc = "Field `SUSP` writer - SUSP field"]
48pub type SUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
49#[doc = "Field `CLRSUSP` reader - CLRSUSP field"]
50pub type CLRSUSP_R = crate::BitReader<bool>;
51#[doc = "Field `CLRSUSP` writer - CLRSUSP field"]
52pub type CLRSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
53#[doc = "Field `RESET` reader - RESET field"]
54pub type RESET_R = crate::BitReader<bool>;
55#[doc = "Field `RESET` writer - RESET field"]
56pub type RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
57#[doc = "Field `POWER` reader - POWER field"]
58pub type POWER_R = crate::BitReader<bool>;
59#[doc = "Field `POWER` writer - POWER field"]
60pub type POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
61#[doc = "Field `SPEED` reader - SPEED field"]
62pub type SPEED_R = crate::BitReader<bool>;
63#[doc = "Field `SPEED` writer - SPEED field"]
64pub type SPEED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
65#[doc = "Field `CONNCHG` reader - CONNCHG field"]
66pub type CONNCHG_R = crate::BitReader<bool>;
67#[doc = "Field `CONNCHG` writer - CONNCHG field"]
68pub type CONNCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
69#[doc = "Field `ENACHG` reader - ENACHG field"]
70pub type ENACHG_R = crate::BitReader<bool>;
71#[doc = "Field `ENACHG` writer - ENACHG field"]
72pub type ENACHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
73#[doc = "Field `SUSPCHG` reader - SUSPCHG field"]
74pub type SUSPCHG_R = crate::BitReader<bool>;
75#[doc = "Field `SUSPCHG` writer - SUSPCHG field"]
76pub type SUSPCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
77#[doc = "Field `RSTCHG` reader - RSTCHG field"]
78pub type RSTCHG_R = crate::BitReader<bool>;
79#[doc = "Field `RSTCHG` writer - RSTCHG field"]
80pub type RSTCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, PORTSR_SPEC, bool, O>;
81impl R {
82 #[doc = "Bit 0 - CONN field"]
83 #[inline(always)]
84 pub fn conn(&self) -> CONN_R {
85 CONN_R::new((self.bits & 1) != 0)
86 }
87 #[doc = "Bit 1 - ENA field"]
88 #[inline(always)]
89 pub fn ena(&self) -> ENA_R {
90 ENA_R::new(((self.bits >> 1) & 1) != 0)
91 }
92 #[doc = "Bit 2 - SUSP field"]
93 #[inline(always)]
94 pub fn susp(&self) -> SUSP_R {
95 SUSP_R::new(((self.bits >> 2) & 1) != 0)
96 }
97 #[doc = "Bit 3 - CLRSUSP field"]
98 #[inline(always)]
99 pub fn clrsusp(&self) -> CLRSUSP_R {
100 CLRSUSP_R::new(((self.bits >> 3) & 1) != 0)
101 }
102 #[doc = "Bit 4 - RESET field"]
103 #[inline(always)]
104 pub fn reset(&self) -> RESET_R {
105 RESET_R::new(((self.bits >> 4) & 1) != 0)
106 }
107 #[doc = "Bit 8 - POWER field"]
108 #[inline(always)]
109 pub fn power(&self) -> POWER_R {
110 POWER_R::new(((self.bits >> 8) & 1) != 0)
111 }
112 #[doc = "Bit 9 - SPEED field"]
113 #[inline(always)]
114 pub fn speed(&self) -> SPEED_R {
115 SPEED_R::new(((self.bits >> 9) & 1) != 0)
116 }
117 #[doc = "Bit 16 - CONNCHG field"]
118 #[inline(always)]
119 pub fn connchg(&self) -> CONNCHG_R {
120 CONNCHG_R::new(((self.bits >> 16) & 1) != 0)
121 }
122 #[doc = "Bit 17 - ENACHG field"]
123 #[inline(always)]
124 pub fn enachg(&self) -> ENACHG_R {
125 ENACHG_R::new(((self.bits >> 17) & 1) != 0)
126 }
127 #[doc = "Bit 18 - SUSPCHG field"]
128 #[inline(always)]
129 pub fn suspchg(&self) -> SUSPCHG_R {
130 SUSPCHG_R::new(((self.bits >> 18) & 1) != 0)
131 }
132 #[doc = "Bit 20 - RSTCHG field"]
133 #[inline(always)]
134 pub fn rstchg(&self) -> RSTCHG_R {
135 RSTCHG_R::new(((self.bits >> 20) & 1) != 0)
136 }
137}
138impl W {
139 #[doc = "Bit 0 - CONN field"]
140 #[inline(always)]
141 pub fn conn(&mut self) -> CONN_W<0> {
142 CONN_W::new(self)
143 }
144 #[doc = "Bit 1 - ENA field"]
145 #[inline(always)]
146 pub fn ena(&mut self) -> ENA_W<1> {
147 ENA_W::new(self)
148 }
149 #[doc = "Bit 2 - SUSP field"]
150 #[inline(always)]
151 pub fn susp(&mut self) -> SUSP_W<2> {
152 SUSP_W::new(self)
153 }
154 #[doc = "Bit 3 - CLRSUSP field"]
155 #[inline(always)]
156 pub fn clrsusp(&mut self) -> CLRSUSP_W<3> {
157 CLRSUSP_W::new(self)
158 }
159 #[doc = "Bit 4 - RESET field"]
160 #[inline(always)]
161 pub fn reset(&mut self) -> RESET_W<4> {
162 RESET_W::new(self)
163 }
164 #[doc = "Bit 8 - POWER field"]
165 #[inline(always)]
166 pub fn power(&mut self) -> POWER_W<8> {
167 POWER_W::new(self)
168 }
169 #[doc = "Bit 9 - SPEED field"]
170 #[inline(always)]
171 pub fn speed(&mut self) -> SPEED_W<9> {
172 SPEED_W::new(self)
173 }
174 #[doc = "Bit 16 - CONNCHG field"]
175 #[inline(always)]
176 pub fn connchg(&mut self) -> CONNCHG_W<16> {
177 CONNCHG_W::new(self)
178 }
179 #[doc = "Bit 17 - ENACHG field"]
180 #[inline(always)]
181 pub fn enachg(&mut self) -> ENACHG_W<17> {
182 ENACHG_W::new(self)
183 }
184 #[doc = "Bit 18 - SUSPCHG field"]
185 #[inline(always)]
186 pub fn suspchg(&mut self) -> SUSPCHG_W<18> {
187 SUSPCHG_W::new(self)
188 }
189 #[doc = "Bit 20 - RSTCHG field"]
190 #[inline(always)]
191 pub fn rstchg(&mut self) -> RSTCHG_W<20> {
192 RSTCHG_W::new(self)
193 }
194 #[doc = "Writes raw bits to the register."]
195 #[inline(always)]
196 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197 self.0.bits(bits);
198 self
199 }
200}
201#[doc = "PORTSR register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portsr](index.html) module"]
202pub struct PORTSR_SPEC;
203impl crate::RegisterSpec for PORTSR_SPEC {
204 type Ux = u32;
205}
206#[doc = "`read()` method returns [portsr::R](R) reader structure"]
207impl crate::Readable for PORTSR_SPEC {
208 type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [portsr::W](W) writer structure"]
211impl crate::Writable for PORTSR_SPEC {
212 type Writer = W;
213}
214#[doc = "`reset()` method sets PORTSR to value 0"]
215impl crate::Resettable for PORTSR_SPEC {
216 #[inline(always)]
217 fn reset_value() -> Self::Ux {
218 0
219 }
220}