1#[doc = "Register `CLKSEL` reader"]
2pub struct R(crate::R<CLKSEL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLKSEL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLKSEL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLKSEL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CLKSEL` writer"]
17pub struct W(crate::W<CLKSEL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLKSEL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLKSEL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLKSEL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SYS` reader - SYS field"]
38pub type SYS_R = crate::BitReader<bool>;
39#[doc = "Field `SYS` writer - SYS field"]
40pub type SYS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKSEL_SPEC, bool, O>;
41#[doc = "Field `CLK_DIVx` reader - CLK_DIVx field"]
42pub type CLK_DIVX_R = crate::BitReader<bool>;
43#[doc = "Field `CLK_DIVx` writer - CLK_DIVx field"]
44pub type CLK_DIVX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKSEL_SPEC, bool, O>;
45#[doc = "Field `CLK` reader - CLK field"]
46pub type CLK_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `CLK` writer - CLK field"]
48pub type CLK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 3, O>;
49#[doc = "Field `RTC` reader - RTC field"]
50pub type RTC_R = crate::BitReader<bool>;
51#[doc = "Field `RTC` writer - RTC field"]
52pub type RTC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKSEL_SPEC, bool, O>;
53#[doc = "Field `IOFILT` reader - IOFILT field"]
54pub type IOFILT_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `IOFILT` writer - IOFILT field"]
56pub type IOFILT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
57#[doc = "Field `SDIO` reader - SDIO field"]
58pub type SDIO_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `SDIO` writer - SDIO field"]
60pub type SDIO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
61#[doc = "Field `WDT` reader - WDT field"]
62pub type WDT_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `WDT` writer - WDT field"]
64pub type WDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
65#[doc = "Field `AD0` reader - AD0 field"]
66pub type AD0_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `AD0` writer - AD0 field"]
68pub type AD0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
69#[doc = "Field `AD0DIV` reader - AD0DIV field"]
70pub type AD0DIV_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `AD0DIV` writer - AD0DIV field"]
72pub type AD0DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
73#[doc = "Field `AD1` reader - AD1 field"]
74pub type AD1_R = crate::FieldReader<u8, u8>;
75#[doc = "Field `AD1` writer - AD1 field"]
76pub type AD1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
77#[doc = "Field `AD1DIV` reader - AD1DIV field"]
78pub type AD1DIV_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `AD1DIV` writer - AD1DIV field"]
80pub type AD1DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKSEL_SPEC, u8, u8, 2, O>;
81#[doc = "Field `SLEEP` reader - SLEEP field"]
82pub type SLEEP_R = crate::BitReader<bool>;
83#[doc = "Field `SLEEP` writer - SLEEP field"]
84pub type SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKSEL_SPEC, bool, O>;
85impl R {
86 #[doc = "Bit 0 - SYS field"]
87 #[inline(always)]
88 pub fn sys(&self) -> SYS_R {
89 SYS_R::new((self.bits & 1) != 0)
90 }
91 #[doc = "Bit 1 - CLK_DIVx field"]
92 #[inline(always)]
93 pub fn clk_divx(&self) -> CLK_DIVX_R {
94 CLK_DIVX_R::new(((self.bits >> 1) & 1) != 0)
95 }
96 #[doc = "Bits 2:4 - CLK field"]
97 #[inline(always)]
98 pub fn clk(&self) -> CLK_R {
99 CLK_R::new(((self.bits >> 2) & 7) as u8)
100 }
101 #[doc = "Bit 5 - RTC field"]
102 #[inline(always)]
103 pub fn rtc(&self) -> RTC_R {
104 RTC_R::new(((self.bits >> 5) & 1) != 0)
105 }
106 #[doc = "Bits 6:7 - IOFILT field"]
107 #[inline(always)]
108 pub fn iofilt(&self) -> IOFILT_R {
109 IOFILT_R::new(((self.bits >> 6) & 3) as u8)
110 }
111 #[doc = "Bits 10:11 - SDIO field"]
112 #[inline(always)]
113 pub fn sdio(&self) -> SDIO_R {
114 SDIO_R::new(((self.bits >> 10) & 3) as u8)
115 }
116 #[doc = "Bits 12:13 - WDT field"]
117 #[inline(always)]
118 pub fn wdt(&self) -> WDT_R {
119 WDT_R::new(((self.bits >> 12) & 3) as u8)
120 }
121 #[doc = "Bits 16:17 - AD0 field"]
122 #[inline(always)]
123 pub fn ad0(&self) -> AD0_R {
124 AD0_R::new(((self.bits >> 16) & 3) as u8)
125 }
126 #[doc = "Bits 18:19 - AD0DIV field"]
127 #[inline(always)]
128 pub fn ad0div(&self) -> AD0DIV_R {
129 AD0DIV_R::new(((self.bits >> 18) & 3) as u8)
130 }
131 #[doc = "Bits 20:21 - AD1 field"]
132 #[inline(always)]
133 pub fn ad1(&self) -> AD1_R {
134 AD1_R::new(((self.bits >> 20) & 3) as u8)
135 }
136 #[doc = "Bits 22:23 - AD1DIV field"]
137 #[inline(always)]
138 pub fn ad1div(&self) -> AD1DIV_R {
139 AD1DIV_R::new(((self.bits >> 22) & 3) as u8)
140 }
141 #[doc = "Bit 24 - SLEEP field"]
142 #[inline(always)]
143 pub fn sleep(&self) -> SLEEP_R {
144 SLEEP_R::new(((self.bits >> 24) & 1) != 0)
145 }
146}
147impl W {
148 #[doc = "Bit 0 - SYS field"]
149 #[inline(always)]
150 pub fn sys(&mut self) -> SYS_W<0> {
151 SYS_W::new(self)
152 }
153 #[doc = "Bit 1 - CLK_DIVx field"]
154 #[inline(always)]
155 pub fn clk_divx(&mut self) -> CLK_DIVX_W<1> {
156 CLK_DIVX_W::new(self)
157 }
158 #[doc = "Bits 2:4 - CLK field"]
159 #[inline(always)]
160 pub fn clk(&mut self) -> CLK_W<2> {
161 CLK_W::new(self)
162 }
163 #[doc = "Bit 5 - RTC field"]
164 #[inline(always)]
165 pub fn rtc(&mut self) -> RTC_W<5> {
166 RTC_W::new(self)
167 }
168 #[doc = "Bits 6:7 - IOFILT field"]
169 #[inline(always)]
170 pub fn iofilt(&mut self) -> IOFILT_W<6> {
171 IOFILT_W::new(self)
172 }
173 #[doc = "Bits 10:11 - SDIO field"]
174 #[inline(always)]
175 pub fn sdio(&mut self) -> SDIO_W<10> {
176 SDIO_W::new(self)
177 }
178 #[doc = "Bits 12:13 - WDT field"]
179 #[inline(always)]
180 pub fn wdt(&mut self) -> WDT_W<12> {
181 WDT_W::new(self)
182 }
183 #[doc = "Bits 16:17 - AD0 field"]
184 #[inline(always)]
185 pub fn ad0(&mut self) -> AD0_W<16> {
186 AD0_W::new(self)
187 }
188 #[doc = "Bits 18:19 - AD0DIV field"]
189 #[inline(always)]
190 pub fn ad0div(&mut self) -> AD0DIV_W<18> {
191 AD0DIV_W::new(self)
192 }
193 #[doc = "Bits 20:21 - AD1 field"]
194 #[inline(always)]
195 pub fn ad1(&mut self) -> AD1_W<20> {
196 AD1_W::new(self)
197 }
198 #[doc = "Bits 22:23 - AD1DIV field"]
199 #[inline(always)]
200 pub fn ad1div(&mut self) -> AD1DIV_W<22> {
201 AD1DIV_W::new(self)
202 }
203 #[doc = "Bit 24 - SLEEP field"]
204 #[inline(always)]
205 pub fn sleep(&mut self) -> SLEEP_W<24> {
206 SLEEP_W::new(self)
207 }
208 #[doc = "Writes raw bits to the register."]
209 #[inline(always)]
210 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
211 self.0.bits(bits);
212 self
213 }
214}
215#[doc = "CLKSEL register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clksel](index.html) module"]
216pub struct CLKSEL_SPEC;
217impl crate::RegisterSpec for CLKSEL_SPEC {
218 type Ux = u32;
219}
220#[doc = "`read()` method returns [clksel::R](R) reader structure"]
221impl crate::Readable for CLKSEL_SPEC {
222 type Reader = R;
223}
224#[doc = "`write(|w| ..)` method takes [clksel::W](W) writer structure"]
225impl crate::Writable for CLKSEL_SPEC {
226 type Writer = W;
227}
228#[doc = "`reset()` method sets CLKSEL to value 0"]
229impl crate::Resettable for CLKSEL_SPEC {
230 #[inline(always)]
231 fn reset_value() -> Self::Ux {
232 0
233 }
234}