swage_core/memory/
mem_configuration.rs

1use crate::util::ROW_SHIFT;
2use serde::Deserialize;
3
4/// Size of DRAM addressing matrices
5pub const MTX_SIZE: usize = 30;
6
7/// DRAM addressing configuration.
8///
9/// Defines how virtual addresses map to physical DRAM organization
10/// (bank, row, column) using transformation matrices.
11#[derive(Deserialize, Debug, Copy, Clone, Default, PartialEq, Eq)]
12pub struct MemConfiguration {
13    /// Bit shift for bank extraction
14    pub bk_shift: usize,
15    /// Bit mask for bank extraction
16    pub bk_mask: usize,
17    /// Bit shift for row extraction
18    pub row_shift: usize,
19    /// Bit mask for row extraction
20    pub row_mask: usize,
21    /// Bit shift for column extraction
22    pub col_shift: usize,
23    /// Bit mask for column extraction
24    pub col_mask: usize,
25    /// DRAM addressing matrix (virtual to DRAM)
26    pub dram_mtx: [usize; MTX_SIZE],
27    /// Address reconstruction matrix (DRAM to virtual)
28    pub addr_mtx: [usize; MTX_SIZE],
29    /// Maximum bank bit position
30    pub max_bank_bit: u64,
31}
32
33impl MemConfiguration {
34    /// Returns the periodicity of the bank function in rows.
35    ///
36    /// Indicates how many rows must be iterated before the bank function repeats.
37    pub fn bank_function_period(&self) -> u64 {
38        1 << (self.max_bank_bit + 1 - ROW_SHIFT as u64)
39    }
40}
41
42impl MemConfiguration {
43    /// Returns the number of banks in this DRAM configuration.
44    pub fn get_bank_count(&self) -> usize {
45        (1 << self.bk_mask.count_ones()) as usize
46    }
47
48    /// Returns the number of rows in this DRAM configuration.
49    pub fn get_row_count(&self) -> usize {
50        1_usize << (self.row_mask.count_ones() as usize)
51    }
52}
swage_core/memory/mem_configuration.rs

swage_core/memory/
mem_configuration.rs
