sverilogparse/
lib.rs

1//! A structural verilog parser written in Rust.
2//!
3//! # Usage
4//! 
5//! Just pass an [ArcStr] to [SVerilog::parse_str]. Example:
6//! ```
7//! use sverilogparse::SVerilog;
8//! 
9//! let _parsed = SVerilog::parse_str(arcstr::literal!(r#"
10//! module simple (a, b);
11//! input a;
12//! output b;
13//! not n1 (.a(a), .out(b));
14//! endmodule
15//! "#)).expect("parse error");
16//! ```
17
18use arcstr::{ArcStr, Substr};
19use std::num::Wrapping;
20
21/// Packages all content in structural verilog, in an unmodified manner.
22#[derive(Debug)]
23pub struct SVerilog {
24    /// A vector of module names and parsed module object.
25    pub modules: Vec<(Substr, SVerilogModule)>,
26}
27
28mod range;
29pub use range::SVerilogRange;
30
31/// A wire/io definition with optional vector width.
32#[derive(Debug)]
33pub struct SVerilogWireDef {
34    /// Wire name. E.g. `net0`
35    pub name: Substr,
36    /// Wire width if it is a vector.
37    pub width: Option<SVerilogRange>,
38    /// Wire type.
39    pub typ: WireDefType,
40}
41
42#[derive(Debug, PartialEq, Eq, Clone, Copy)]
43pub enum WireDefType {
44    Input,
45    Output,
46    InOut,
47    Wire
48}
49
50/// A parsed structural verilog module.
51#[derive(Debug)]
52pub struct SVerilogModule {
53    /// Module ports.
54    pub ports: Vec<SVerilogPortDef>,
55    /// Module I/O and net definitions.
56    pub defs: Vec<SVerilogWireDef>,
57    /// Assignment operations in the module body.
58    pub assigns: Vec<SVerilogAssign>,
59    /// Cells in the module body.
60    pub cells: Vec<SVerilogCell>,
61}
62
63/// A port definition. Can be either a single identifier, or
64/// a named port connection like `.gpio({g1, g2, g3})`.
65#[derive(Debug)]
66pub enum SVerilogPortDef {
67    /// E.g. `gpio`.
68    Basic(Substr),
69    /// E.g. `.gpio({g1, g2, g3})`.
70    Conn(Substr, Wirexpr)
71}
72
73/// Basic component of a wire expression, which can be
74/// a wire reference, reference to a single wire bit,
75/// slice of a wire vector, or a constant literal.
76#[derive(Debug, PartialEq)]
77pub enum WirexprBasic {
78    /// E.g. `somepin`.
79    Full(Substr),
80    /// E.g. `somepin[1]`.
81    SingleBit(Substr, isize),
82    /// E.g. `somepin[0:7]`.
83    Slice(Substr, SVerilogRange),
84    /// E.g. `4'b01xz`.
85    /// The pairs are (size, value, is\_xz).
86    Literal(usize, u128, u128),
87}
88
89/// A wire expression containing either a basic component or a
90/// concatenation of multiple basic components.
91#[derive(Debug)]
92pub enum Wirexpr {
93    /// A single basic component.
94    Basic(WirexprBasic),
95    /// Multiple basic components enclosed in curly braces.
96    /// E.g. `{somepin, 1'b0, otherpin[0:7]}`.
97    Concat(Vec<WirexprBasic>),
98}
99
100/// An assign operation.
101#[derive(Debug)]
102pub struct SVerilogAssign {
103    /// Left-hand side expr.
104    pub lhs: Wirexpr,
105    /// Right-hand side expr.
106    pub rhs: Wirexpr,
107}
108
109/// A parsed cell instantiation in structural verilog.
110#[derive(Debug)]
111pub struct SVerilogCell {
112    /// The name of macro. E.g. `NAND`.
113    pub macro_name: Substr,
114    /// The name of cell. E.g. `nand01`.
115    pub cell_name: Substr,
116    /// contains tuples of (macro_pin_name, wire_name).
117    pub ioports: Vec<(Substr, Wirexpr)>,
118}
119
120mod sverilogpest;
121
122impl SVerilog {
123    /// Parses a string ([ArcStr]) of structural verilog code, and returns a [Result], indicating successful parse result or an error string.
124    #[inline]
125    pub fn parse_str(s: ArcStr) -> Result<SVerilog, String> {
126        sverilogpest::parse_sverilog(s)
127    }
128}
129
130mod fmt;
sverilogparse/lib.rs

sverilogparse/
lib.rs
