Crate sverilogparse

A structural verilog parser written in Rust.

Usage

Just pass an ArcStr to SVerilog::parse_str. Example:

use sverilogparse::SVerilog;
 
let _parsed = SVerilog::parse_str(arcstr::literal!(r#"
module simple (a, b);
input a;
output b;
not n1 (.a(a), .out(b));
endmodule
"#)).expect("parse error");

Structs

SVerilog

Packages all content in structural verilog, in an unmodified manner.

SVerilogCell

A parsed cell instantiation in structural verilog.

SVerilogModule

A parsed structural verilog module.

SVerilogWireDef

A wire/io definition with optional vector width.

Enums

WireDefType

Wirexpr

A wire expression containing either a basic component or a concatenation of multiple basic components.

WirexprBasic

Basic component of a wire expression, which can be a wire reference, reference to a single wire bit, slice of a wire vector, or a constant literal.