Crate sverilogparse
source · [−]Expand description
A structural verilog parser written in Rust.
Usage
Just pass an ArcStr to SVerilog::parse_str. Example:
use sverilogparse::SVerilog;
let _parsed = SVerilog::parse_str(arcstr::literal!(r#"
module simple (a, b);
input a;
output b;
not n1 (.a(a), .out(b));
endmodule
"#)).expect("parse error");
Structs
Packages all content in structural verilog, in an unmodified manner.
A parsed cell instantiation in structural verilog.
A parsed structural verilog module.
A wire/io definition with optional vector width.
Enums
A wire expression containing either a basic component or a concatenation of multiple basic components.
Basic component of a wire expression, which can be a wire reference, reference to a single wire bit, slice of a wire vector, or a constant literal.