Expand description
A structural verilog parser written in Rust.
§Usage
Just pass an ArcStr to SVerilog::parse_str. Example:
use sverilogparse::SVerilog;
let _parsed = SVerilog::parse_str(arcstr::literal!(r#"
module simple (a, b);
input a;
output b;
not n1 (.a(a), .out(b));
endmodule
"#)).expect("parse error");Structs§
- SVerilog
- Packages all content in structural verilog, in an unmodified manner.
- SVerilog
Assign - An assign operation.
- SVerilog
Cell - A parsed cell instantiation in structural verilog.
- SVerilog
Module - A parsed structural verilog module.
- SVerilog
Range - An inclusive range in verilog.
- SVerilog
Wire Def - A wire/io definition with optional vector width.
Enums§
- SVerilog
Port Def - A port definition. Can be either a single identifier, or
a named port connection like
.gpio({g1, g2, g3}). - Wire
DefType - Wirexpr
- A wire expression containing either a basic component or a concatenation of multiple basic components.
- Wirexpr
Basic - Basic component of a wire expression, which can be a wire reference, reference to a single wire bit, slice of a wire vector, or a constant literal.