Crate sverilogparse

Source
Expand description

A structural verilog parser written in Rust.

§Usage

Just pass an ArcStr to SVerilog::parse_str. Example:

use sverilogparse::SVerilog;
 
let _parsed = SVerilog::parse_str(arcstr::literal!(r#"
module simple (a, b);
input a;
output b;
not n1 (.a(a), .out(b));
endmodule
"#)).expect("parse error");

Structs§

SVerilog
Packages all content in structural verilog, in an unmodified manner.
SVerilogAssign
An assign operation.
SVerilogCell
A parsed cell instantiation in structural verilog.
SVerilogModule
A parsed structural verilog module.
SVerilogRange
An inclusive range in verilog.
SVerilogWireDef
A wire/io definition with optional vector width.

Enums§

SVerilogPortDef
A port definition. Can be either a single identifier, or a named port connection like .gpio({g1, g2, g3}).
WireDefType
Wirexpr
A wire expression containing either a basic component or a concatenation of multiple basic components.
WirexprBasic
Basic component of a wire expression, which can be a wire reference, reference to a single wire bit, slice of a wire vector, or a constant literal.