Module cache_ops 

Cache-line stewardship: instruction-level hints the compiler never emits on its own.

LLVM treats every store identically; it has no model of WHICH core reads a line next. These wrappers encode that knowledge at the three points the substrate has it:

op	when	effect
prefetchw	before a CAS/RMW on a contended line	requests the line in Modified state, collapsing the read-for-ownership round trip the CAS pays otherwise
cldemote	after the producer publishes a slot + sequence	pushes the just-written line toward the shared LLC so the consumer’s first read is an LLC hit, not a cross-core snoop-and-forward
sfence	after non-temporal stores, before the Release publish	orders weakly-ordered streaming stores ahead of the sequence store other cores acquire on

Safety/portability posture (per the project’s fallback mandate): every op compiles to a plain no-op on non-x86_64 targets, and on x86_64 each is either architecturally NOP-safe on silicon that lacks it or baseline-guaranteed:

• PREFETCHW (0F 0D /1): prefetch hints never fault; AMD since K6, Intel since Broadwell, and pre-Broadwell Intel executes the encoding as a NOP (it sits in the NOP-reserved hint space).
• CLDEMOTE (NP 0F 1C /0): per the Intel ISA reference, “on processors which do not support the CLDEMOTE instruction (including legacy hardware) the instruction will be treated as a NOP”. CPUID 7.0 ECX bit 25 reports real support (has_cldemote) for diagnostics; execution needs no gate.
• SFENCE is baseline x86-64 (SSE2).

Both hint wrappers are emitted as explicit byte sequences, not mnemonics, so the assembler never gates them behind target features the baseline build does not enable.

Functions

cldemote

Demote the cache line containing addr toward the shared LLC. Call after the producer’s final store to a line whose next reader is another core (slot payload, published sequence). Architecturally a NOP wherever unsupported; the hint may also be ignored by hardware - it is never load-bearing.

has_cldemote

Whether this CPU actually implements CLDEMOTE (CPUID 7.0 ECX bit 25). Diagnostic only - cldemote is NOP-safe regardless.

prefetchw

Write-intent prefetch of the cache line containing addr. Call immediately before a compare_exchange / fetch_* on a line another core probably owns: the line arrives in Modified state instead of being upgraded mid-RMW.

sfence

Store fence: orders all prior stores (including non-temporal ones, which Release ordering alone does NOT cover) before any later store. Required between a streaming copy and the sequence-publish store that makes it visible.