Module cpuid 

Tiny CPUID feature-detection surface that adaptive primitives across the SubEtha workspace consult to gate hardware-acceleration paths.

The substrate exposes:

• has_waitpkg - is the WAITPKG ISA extension (UMONITOR / UMWAIT / TPAUSE) available?
• has_movdir64b - is the MOVDIR64B ISA extension (atomic non-temporal 64-byte cache-line store) available?

WAITPKG was introduced on Intel Tremont (2019) and Tiger Lake (2020) microarchitectures, and on AMD Zen 5 (2024). Hosts older than that need a PAUSE-spin fallback; primitives that wait on a cache line (e.g. SharedDequeUrd in subetha-cxc) pick the wait strategy at runtime by calling this function once and caching the result.

MOVDIR64B was introduced on Intel Tremont (2019) and Tiger Lake (2020), and on AMD Zen 5 (2024). It is the atomic 64-byte non-temporal store; SharedDequeUrd uses it to publish a whole mailbox line in one transaction, eliminating the cross-CCX coherence-upgrade traffic that the byte-by-byte fallback path pays on hosts without it.

Both flags are probed via CPUID leaf 7 sub-leaf 0 (Structured Extended Feature Flags): ECX bit 5 = WAITPKG, ECX bit 28 = MOVDIR64B.

Functions

has_movdir64b

Returns true when the CPU advertises the MOVDIR64B ISA extension (atomic non-temporal 64-byte cache-line store).

has_waitpkg

Returns true when the CPU advertises the WAITPKG ISA extension (UMONITOR / UMWAIT / TPAUSE).