stm32wl/stm32wl5x_cm4/
tzsc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    _reserved1: [u8; 0x0c],
7    seccfgr1: SECCFGR1,
8    _reserved2: [u8; 0x0c],
9    privcfgr1: PRIVCFGR1,
10    _reserved3: [u8; 0x010c],
11    mpcwm1_upwmr: MPCWM1_UPWMR,
12    mpcwm1_upwwmr: MPCWM1_UPWWMR,
13    mpcwm2_upwmr: MPCWM2_UPWMR,
14    _reserved6: [u8; 0x04],
15    mpcwm3_upwmr: MPCWM3_UPWMR,
16}
17impl RegisterBlock {
18    ///0x00 - TZSC control register
19    #[inline(always)]
20    pub const fn cr(&self) -> &CR {
21        &self.cr
22    }
23    ///0x10 - TZSC security configuration register
24    #[inline(always)]
25    pub const fn seccfgr1(&self) -> &SECCFGR1 {
26        &self.seccfgr1
27    }
28    ///0x20 - TZSC privilege configuration register 1
29    #[inline(always)]
30    pub const fn privcfgr1(&self) -> &PRIVCFGR1 {
31        &self.privcfgr1
32    }
33    ///0x130 - Unprivileged Water Mark 1 register
34    #[inline(always)]
35    pub const fn mpcwm1_upwmr(&self) -> &MPCWM1_UPWMR {
36        &self.mpcwm1_upwmr
37    }
38    ///0x134 - Unprivileged Writable Water Mark 1 register
39    #[inline(always)]
40    pub const fn mpcwm1_upwwmr(&self) -> &MPCWM1_UPWWMR {
41        &self.mpcwm1_upwwmr
42    }
43    ///0x138 - Unprivileged Water Mark 2 register
44    #[inline(always)]
45    pub const fn mpcwm2_upwmr(&self) -> &MPCWM2_UPWMR {
46        &self.mpcwm2_upwmr
47    }
48    ///0x140 - Unprivileged Water Mark 3 register
49    #[inline(always)]
50    pub const fn mpcwm3_upwmr(&self) -> &MPCWM3_UPWMR {
51        &self.mpcwm3_upwmr
52    }
53}
54/**CR (rw) register accessor: TZSC control register
55
56You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
57
58See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:CR)
59
60For information about available fields see [`mod@cr`] module*/
61pub type CR = crate::Reg<cr::CRrs>;
62///TZSC control register
63pub mod cr;
64/**SECCFGR1 (rw) register accessor: TZSC security configuration register
65
66You can [`read`](crate::Reg::read) this register and get [`seccfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
67
68See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:SECCFGR1)
69
70For information about available fields see [`mod@seccfgr1`] module*/
71pub type SECCFGR1 = crate::Reg<seccfgr1::SECCFGR1rs>;
72///TZSC security configuration register
73pub mod seccfgr1;
74/**PRIVCFGR1 (rw) register accessor: TZSC privilege configuration register 1
75
76You can [`read`](crate::Reg::read) this register and get [`privcfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`privcfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
77
78See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:PRIVCFGR1)
79
80For information about available fields see [`mod@privcfgr1`] module*/
81pub type PRIVCFGR1 = crate::Reg<privcfgr1::PRIVCFGR1rs>;
82///TZSC privilege configuration register 1
83pub mod privcfgr1;
84/**MPCWM1_UPWMR (rw) register accessor: Unprivileged Water Mark 1 register
85
86You can [`read`](crate::Reg::read) this register and get [`mpcwm1_upwmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpcwm1_upwmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
87
88See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:MPCWM1_UPWMR)
89
90For information about available fields see [`mod@mpcwm1_upwmr`] module*/
91pub type MPCWM1_UPWMR = crate::Reg<mpcwm1_upwmr::MPCWM1_UPWMRrs>;
92///Unprivileged Water Mark 1 register
93pub mod mpcwm1_upwmr;
94/**MPCWM1_UPWWMR (rw) register accessor: Unprivileged Writable Water Mark 1 register
95
96You can [`read`](crate::Reg::read) this register and get [`mpcwm1_upwwmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpcwm1_upwwmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
97
98See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:MPCWM1_UPWWMR)
99
100For information about available fields see [`mod@mpcwm1_upwwmr`] module*/
101pub type MPCWM1_UPWWMR = crate::Reg<mpcwm1_upwwmr::MPCWM1_UPWWMRrs>;
102///Unprivileged Writable Water Mark 1 register
103pub mod mpcwm1_upwwmr;
104/**MPCWM2_UPWMR (rw) register accessor: Unprivileged Water Mark 2 register
105
106You can [`read`](crate::Reg::read) this register and get [`mpcwm2_upwmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpcwm2_upwmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
107
108See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:MPCWM2_UPWMR)
109
110For information about available fields see [`mod@mpcwm2_upwmr`] module*/
111pub type MPCWM2_UPWMR = crate::Reg<mpcwm2_upwmr::MPCWM2_UPWMRrs>;
112///Unprivileged Water Mark 2 register
113pub mod mpcwm2_upwmr;
114/**MPCWM3_UPWMR (rw) register accessor: Unprivileged Water Mark 3 register
115
116You can [`read`](crate::Reg::read) this register and get [`mpcwm3_upwmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpcwm3_upwmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
117
118See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TZSC:MPCWM3_UPWMR)
119
120For information about available fields see [`mod@mpcwm3_upwmr`] module*/
121pub type MPCWM3_UPWMR = crate::Reg<mpcwm3_upwmr::MPCWM3_UPWMRrs>;
122///Unprivileged Water Mark 3 register
123pub mod mpcwm3_upwmr;
stm32wl/stm32wl5x_cm4/tzsc.rs

stm32wl/stm32wl5x_cm4/
tzsc.rs
