stm32wl/stm32wl5x_cm4/rcc/
extcfgr.rs

1///Register `EXTCFGR` reader
2pub type R = crate::R<EXTCFGRrs>;
3///Register `EXTCFGR` writer
4pub type W = crate::W<EXTCFGRrs>;
5/**HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum SHDHPRE {
12    ///1: SYSCLK divided by 3
13    Div3 = 1,
14    ///2: SYSCLK divided by 5
15    Div5 = 2,
16    ///5: SYSCLK divided by 6
17    Div6 = 5,
18    ///6: SYSCLK divided by 10
19    Div10 = 6,
20    ///7: SYSCLK divided by 32
21    Div32 = 7,
22    ///8: SYSCLK divided by 2
23    Div2 = 8,
24    ///9: SYSCLK divided by 4
25    Div4 = 9,
26    ///10: SYSCLK divided by 8
27    Div8 = 10,
28    ///11: SYSCLK divided by 16
29    Div16 = 11,
30    ///12: SYSCLK divided by 64
31    Div64 = 12,
32    ///13: SYSCLK divided by 128
33    Div128 = 13,
34    ///14: SYSCLK divided by 256
35    Div256 = 14,
36    ///15: SYSCLK divided by 512
37    Div512 = 15,
38    ///0: SYSCLK not divided
39    Div1 = 0,
40}
41impl From<SHDHPRE> for u8 {
42    #[inline(always)]
43    fn from(variant: SHDHPRE) -> Self {
44        variant as _
45    }
46}
47impl crate::FieldSpec for SHDHPRE {
48    type Ux = u8;
49}
50impl crate::IsEnum for SHDHPRE {}
51///Field `SHDHPRE` reader - HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
52pub type SHDHPRE_R = crate::FieldReader<SHDHPRE>;
53impl SHDHPRE_R {
54    ///Get enumerated values variant
55    #[inline(always)]
56    pub const fn variant(&self) -> SHDHPRE {
57        match self.bits {
58            1 => SHDHPRE::Div3,
59            2 => SHDHPRE::Div5,
60            5 => SHDHPRE::Div6,
61            6 => SHDHPRE::Div10,
62            7 => SHDHPRE::Div32,
63            8 => SHDHPRE::Div2,
64            9 => SHDHPRE::Div4,
65            10 => SHDHPRE::Div8,
66            11 => SHDHPRE::Div16,
67            12 => SHDHPRE::Div64,
68            13 => SHDHPRE::Div128,
69            14 => SHDHPRE::Div256,
70            15 => SHDHPRE::Div512,
71            _ => SHDHPRE::Div1,
72        }
73    }
74    ///SYSCLK divided by 3
75    #[inline(always)]
76    pub fn is_div3(&self) -> bool {
77        *self == SHDHPRE::Div3
78    }
79    ///SYSCLK divided by 5
80    #[inline(always)]
81    pub fn is_div5(&self) -> bool {
82        *self == SHDHPRE::Div5
83    }
84    ///SYSCLK divided by 6
85    #[inline(always)]
86    pub fn is_div6(&self) -> bool {
87        *self == SHDHPRE::Div6
88    }
89    ///SYSCLK divided by 10
90    #[inline(always)]
91    pub fn is_div10(&self) -> bool {
92        *self == SHDHPRE::Div10
93    }
94    ///SYSCLK divided by 32
95    #[inline(always)]
96    pub fn is_div32(&self) -> bool {
97        *self == SHDHPRE::Div32
98    }
99    ///SYSCLK divided by 2
100    #[inline(always)]
101    pub fn is_div2(&self) -> bool {
102        *self == SHDHPRE::Div2
103    }
104    ///SYSCLK divided by 4
105    #[inline(always)]
106    pub fn is_div4(&self) -> bool {
107        *self == SHDHPRE::Div4
108    }
109    ///SYSCLK divided by 8
110    #[inline(always)]
111    pub fn is_div8(&self) -> bool {
112        *self == SHDHPRE::Div8
113    }
114    ///SYSCLK divided by 16
115    #[inline(always)]
116    pub fn is_div16(&self) -> bool {
117        *self == SHDHPRE::Div16
118    }
119    ///SYSCLK divided by 64
120    #[inline(always)]
121    pub fn is_div64(&self) -> bool {
122        *self == SHDHPRE::Div64
123    }
124    ///SYSCLK divided by 128
125    #[inline(always)]
126    pub fn is_div128(&self) -> bool {
127        *self == SHDHPRE::Div128
128    }
129    ///SYSCLK divided by 256
130    #[inline(always)]
131    pub fn is_div256(&self) -> bool {
132        *self == SHDHPRE::Div256
133    }
134    ///SYSCLK divided by 512
135    #[inline(always)]
136    pub fn is_div512(&self) -> bool {
137        *self == SHDHPRE::Div512
138    }
139    ///SYSCLK not divided
140    #[inline(always)]
141    pub fn is_div1(&self) -> bool {
142        matches!(self.variant(), SHDHPRE::Div1)
143    }
144}
145///Field `SHDHPRE` writer - HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
146pub type SHDHPRE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, SHDHPRE, crate::Safe>;
147impl<'a, REG> SHDHPRE_W<'a, REG>
148where
149    REG: crate::Writable + crate::RegisterSpec,
150    REG::Ux: From<u8>,
151{
152    ///SYSCLK divided by 3
153    #[inline(always)]
154    pub fn div3(self) -> &'a mut crate::W<REG> {
155        self.variant(SHDHPRE::Div3)
156    }
157    ///SYSCLK divided by 5
158    #[inline(always)]
159    pub fn div5(self) -> &'a mut crate::W<REG> {
160        self.variant(SHDHPRE::Div5)
161    }
162    ///SYSCLK divided by 6
163    #[inline(always)]
164    pub fn div6(self) -> &'a mut crate::W<REG> {
165        self.variant(SHDHPRE::Div6)
166    }
167    ///SYSCLK divided by 10
168    #[inline(always)]
169    pub fn div10(self) -> &'a mut crate::W<REG> {
170        self.variant(SHDHPRE::Div10)
171    }
172    ///SYSCLK divided by 32
173    #[inline(always)]
174    pub fn div32(self) -> &'a mut crate::W<REG> {
175        self.variant(SHDHPRE::Div32)
176    }
177    ///SYSCLK divided by 2
178    #[inline(always)]
179    pub fn div2(self) -> &'a mut crate::W<REG> {
180        self.variant(SHDHPRE::Div2)
181    }
182    ///SYSCLK divided by 4
183    #[inline(always)]
184    pub fn div4(self) -> &'a mut crate::W<REG> {
185        self.variant(SHDHPRE::Div4)
186    }
187    ///SYSCLK divided by 8
188    #[inline(always)]
189    pub fn div8(self) -> &'a mut crate::W<REG> {
190        self.variant(SHDHPRE::Div8)
191    }
192    ///SYSCLK divided by 16
193    #[inline(always)]
194    pub fn div16(self) -> &'a mut crate::W<REG> {
195        self.variant(SHDHPRE::Div16)
196    }
197    ///SYSCLK divided by 64
198    #[inline(always)]
199    pub fn div64(self) -> &'a mut crate::W<REG> {
200        self.variant(SHDHPRE::Div64)
201    }
202    ///SYSCLK divided by 128
203    #[inline(always)]
204    pub fn div128(self) -> &'a mut crate::W<REG> {
205        self.variant(SHDHPRE::Div128)
206    }
207    ///SYSCLK divided by 256
208    #[inline(always)]
209    pub fn div256(self) -> &'a mut crate::W<REG> {
210        self.variant(SHDHPRE::Div256)
211    }
212    ///SYSCLK divided by 512
213    #[inline(always)]
214    pub fn div512(self) -> &'a mut crate::W<REG> {
215        self.variant(SHDHPRE::Div512)
216    }
217    ///SYSCLK not divided
218    #[inline(always)]
219    pub fn div1(self) -> &'a mut crate::W<REG> {
220        self.variant(SHDHPRE::Div1)
221    }
222}
223///Field `C2HPRE` reader - dual core device only\] HCLK2 prescaler (CPU2)
224pub type C2HPRE_R = crate::FieldReader;
225///Field `C2HPRE` writer - dual core device only\] HCLK2 prescaler (CPU2)
226pub type C2HPRE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
227/**HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
228
229Value on reset: 1*/
230#[cfg_attr(feature = "defmt", derive(defmt::Format))]
231#[derive(Clone, Copy, Debug, PartialEq, Eq)]
232pub enum SHDHPREF {
233    ///0: HCLK3 prescaler value not yet applied
234    NotApplied = 0,
235    ///1: HCLK3 prescaler value applied
236    Applied = 1,
237}
238impl From<SHDHPREF> for bool {
239    #[inline(always)]
240    fn from(variant: SHDHPREF) -> Self {
241        variant as u8 != 0
242    }
243}
244///Field `SHDHPREF` reader - HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
245pub type SHDHPREF_R = crate::BitReader<SHDHPREF>;
246impl SHDHPREF_R {
247    ///Get enumerated values variant
248    #[inline(always)]
249    pub const fn variant(&self) -> SHDHPREF {
250        match self.bits {
251            false => SHDHPREF::NotApplied,
252            true => SHDHPREF::Applied,
253        }
254    }
255    ///HCLK3 prescaler value not yet applied
256    #[inline(always)]
257    pub fn is_not_applied(&self) -> bool {
258        *self == SHDHPREF::NotApplied
259    }
260    ///HCLK3 prescaler value applied
261    #[inline(always)]
262    pub fn is_applied(&self) -> bool {
263        *self == SHDHPREF::Applied
264    }
265}
266///Field `C2HPREF` reader - CLK2 prescaler flag (CPU2)
267pub type C2HPREF_R = crate::BitReader;
268impl R {
269    ///Bits 0:3 - HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
270    #[inline(always)]
271    pub fn shdhpre(&self) -> SHDHPRE_R {
272        SHDHPRE_R::new((self.bits & 0x0f) as u8)
273    }
274    ///Bits 4:7 - dual core device only\] HCLK2 prescaler (CPU2)
275    #[inline(always)]
276    pub fn c2hpre(&self) -> C2HPRE_R {
277        C2HPRE_R::new(((self.bits >> 4) & 0x0f) as u8)
278    }
279    ///Bit 16 - HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
280    #[inline(always)]
281    pub fn shdhpref(&self) -> SHDHPREF_R {
282        SHDHPREF_R::new(((self.bits >> 16) & 1) != 0)
283    }
284    ///Bit 17 - CLK2 prescaler flag (CPU2)
285    #[inline(always)]
286    pub fn c2hpref(&self) -> C2HPREF_R {
287        C2HPREF_R::new(((self.bits >> 17) & 1) != 0)
288    }
289}
290impl core::fmt::Debug for R {
291    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
292        f.debug_struct("EXTCFGR")
293            .field("c2hpref", &self.c2hpref())
294            .field("shdhpref", &self.shdhpref())
295            .field("c2hpre", &self.c2hpre())
296            .field("shdhpre", &self.shdhpre())
297            .finish()
298    }
299}
300impl W {
301    ///Bits 0:3 - HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
302    #[inline(always)]
303    pub fn shdhpre(&mut self) -> SHDHPRE_W<EXTCFGRrs> {
304        SHDHPRE_W::new(self, 0)
305    }
306    ///Bits 4:7 - dual core device only\] HCLK2 prescaler (CPU2)
307    #[inline(always)]
308    pub fn c2hpre(&mut self) -> C2HPRE_W<EXTCFGRrs> {
309        C2HPRE_W::new(self, 4)
310    }
311}
312/**Extended clock recovery register
313
314You can [`read`](crate::Reg::read) this register and get [`extcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
315
316See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#RCC:EXTCFGR)*/
317pub struct EXTCFGRrs;
318impl crate::RegisterSpec for EXTCFGRrs {
319    type Ux = u32;
320}
321///`read()` method returns [`extcfgr::R`](R) reader structure
322impl crate::Readable for EXTCFGRrs {}
323///`write(|w| ..)` method takes [`extcfgr::W`](W) writer structure
324impl crate::Writable for EXTCFGRrs {
325    type Safety = crate::Unsafe;
326}
327///`reset()` method sets EXTCFGR to value 0x0003_0000
328impl crate::Resettable for EXTCFGRrs {
329    const RESET_VALUE: u32 = 0x0003_0000;
330}
stm32wl/stm32wl5x_cm4/rcc/extcfgr.rs

stm32wl/stm32wl5x_cm4/rcc/
extcfgr.rs
