Expand description
Field SMS
writer - Slave mode selection
Implementations
sourceimpl<'a, const O: u8> SMS_W<'a, O>
impl<'a, const O: u8> SMS_W<'a, O>
sourcepub fn disabled_or_combined(self) -> &'a mut W
pub fn disabled_or_combined(self) -> &'a mut W
Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter
sourcepub fn encoder_mode1(self) -> &'a mut W
pub fn encoder_mode1(self) -> &'a mut W
Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level
sourcepub fn encoder_mode2(self) -> &'a mut W
pub fn encoder_mode2(self) -> &'a mut W
Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level
sourcepub fn encoder_mode3(self) -> &'a mut W
pub fn encoder_mode3(self) -> &'a mut W
Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input
sourcepub fn reset_mode(self) -> &'a mut W
pub fn reset_mode(self) -> &'a mut W
Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers
sourcepub fn gated_mode(self) -> &'a mut W
pub fn gated_mode(self) -> &'a mut W
Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled
sourcepub fn trigger_mode(self) -> &'a mut W
pub fn trigger_mode(self) -> &'a mut W
Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled
sourcepub fn ext_clock_mode(self) -> &'a mut W
pub fn ext_clock_mode(self) -> &'a mut W
External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter